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ac/surface/tests: add gfx12 tests

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Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29007>
This commit is contained in:
Marek Olšák 2024-03-04 05:06:35 -05:00
parent d22564d29c
commit c8ad0f0715
3 changed files with 86 additions and 6 deletions
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7
src/amd/common/ac_surface_meta_address_test.c
View file

@ -711,6 +711,9 @@ int main(int argc, char **argv)
for (unsigned i = 0; i < ARRAY_SIZE(testcases); ++i) {
struct radeon_info info = get_radeon_info(&testcases[i]);
if (info.gfx_level >= GFX12)
continue;
run_dcc_address_test(testcases[i].name, &info, full);
}
@ -718,8 +721,8 @@ int main(int argc, char **argv)
for (unsigned i = 0; i < ARRAY_SIZE(testcases); ++i) {
struct radeon_info info = get_radeon_info(&testcases[i]);
/* Only GFX10+ is currently supported. */
if (info.gfx_level < GFX10)
/* Only GFX10+ is currently supported. GFX12 doesn't have HTILE. */
if (info.gfx_level < GFX10 || info.gfx_level >= GFX12)
continue;
run_htile_address_test(testcases[i].name, &info, full);

69
src/amd/common/ac_surface_modifier_test.c
View file

@ -201,6 +201,57 @@ static void gfx9_generate_hash(struct ac_addrlib *ac_addrlib,
_mesa_sha1_final(&ctx, entry->hash);
}
static void gfx12_generate_hash(struct ac_addrlib *ac_addrlib,
struct test_entry *entry,
const struct radeon_surf *surf)
{
ADDR_HANDLE addrlib = ac_addrlib_get_handle(ac_addrlib);
srandom(53);
struct mesa_sha1 ctx;
_mesa_sha1_init(&ctx);
_mesa_sha1_update(&ctx, &surf->total_size, sizeof(surf->total_size));
/* We need to hash these even though they are not used by gfx12. */
_mesa_sha1_update(&ctx, &surf->meta_offset, sizeof(surf->meta_offset));
_mesa_sha1_update(&ctx, &surf->display_dcc_offset, sizeof(surf->display_dcc_offset));
_mesa_sha1_update(&ctx, &surf->u.gfx9.color.display_dcc_pitch_max,
sizeof(surf->u.gfx9.color.display_dcc_pitch_max));
ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT input = {0};
input.size = sizeof(input);
input.swizzleMode = surf->u.gfx9.swizzle_mode;
input.flags.color = 1;
input.flags.texture = 1;
input.resourceType = ADDR_RSRC_TEX_2D;
input.bpp = util_format_get_blocksizebits(entry->format);
input.unAlignedDims.width = entry->w;
input.unAlignedDims.height = entry->h;
input.unAlignedDims.depth = 1;
input.numMipLevels = 1;
input.numSamples = 1;
input.pitchInElement = surf->u.gfx9.surf_pitch;
for (unsigned i = 0; i < 1000; ++i) {
int32_t x, y;
x = random();
y = random();
input.x = (x & INT_MAX) % entry->w;
input.y = (y & INT_MAX) % entry->h;
ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT output = {0};
output.size = sizeof(output);
ADDR_E_RETURNCODE ret = Addr3ComputeSurfaceAddrFromCoord(addrlib, &input, &output);
assert(ret == ADDR_OK);
_mesa_sha1_update(&ctx, &output.addr, sizeof(output.addr));
}
_mesa_sha1_final(&ctx, entry->hash);
}
static void test_modifier(const struct radeon_info *info,
const char *name,
struct ac_addrlib *addrlib,
@ -260,8 +311,14 @@ static void test_modifier(const struct radeon_info *info,
uint64_t surf_size;
unsigned aligned_pitch, aligned_height;
if (modifier != DRM_FORMAT_MOD_LINEAR) {
unsigned block_size_bits =
surf.u.gfx9.swizzle_mode >= ADDR_SW_256KB_Z_X ? 18 : 16;
unsigned block_size_bits;
if (info->gfx_level >= GFX12) {
assert(surf.u.gfx9.swizzle_mode == ADDR3_64KB_2D);
block_size_bits = 16;
} else {
block_size_bits = surf.u.gfx9.swizzle_mode >= ADDR_SW_256KB_Z_X ? 18 : 16;
}
surf_size = block_count(dims[i][0], dims[i][1],
elem_bits, block_size_bits, &aligned_pitch,
@ -294,7 +351,7 @@ static void test_modifier(const struct radeon_info *info,
} else
assert(!surf.display_dcc_offset);
if (ac_modifier_has_dcc(modifier)) {
if (info->gfx_level < GFX12 && ac_modifier_has_dcc(modifier)) {
uint64_t dcc_align = 1;
unsigned block_bits;
if (info->gfx_level >= GFX10) {
@ -332,7 +389,11 @@ static void test_modifier(const struct radeon_info *info,
assert(surf.total_size == expected_offset);
gfx9_generate_hash(addrlib, &entry, &surf);
if (info->gfx_level >= GFX12)
gfx12_generate_hash(addrlib, &entry, &surf);
else
gfx9_generate_hash(addrlib, &entry, &surf);
*(struct test_entry*)u_vector_add(test_entries) = entry;
}
}

16
src/amd/common/ac_surface_test_common.h
View file

@ -135,6 +135,20 @@ static void init_gfx11(struct radeon_info *info)
info->gb_addr_config = 0x00000040; /* Other fields are set by test cases. */
}
static void init_gfx12(struct radeon_info *info)
{
info->family = CHIP_GFX1200;
info->gfx_level = GFX12;
info->family_id = FAMILY_GFX12;
info->chip_external_rev = 0x01;
info->has_graphics = true;
info->tcc_cache_line_size = 256;
info->has_rbplus = true;
info->rbplus_allowed = true;
info->gb_addr_config = 0; /* Other fields are set by test cases. */
}
struct testcase {
const char *name;
gpu_init_func init;
@ -172,6 +186,7 @@ static struct testcase testcases[] = {
{"gfx11_4pipe_2pkr", init_gfx11, 1, 2},
{"gfx11_4pipe_1pkr", init_gfx11, 0, 2},
{"gfx11_2pipe_1pkr", init_gfx11, 0, 1},
{"gfx12_16pipe", init_gfx12, 4, 4},
};
static struct radeon_info get_radeon_info(struct testcase *testcase)
@ -198,6 +213,7 @@ static struct radeon_info get_radeon_info(struct testcase *testcase)
case GFX10:
case GFX10_3:
case GFX11:
case GFX12:
info.gb_addr_config = (info.gb_addr_config &
C_0098F8_NUM_PIPES &
C_0098F8_NUM_PKRS) |