From c8852719d05424b9c3e79be49515fd0915191b22 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 13 May 2024 16:46:02 +0200 Subject: [PATCH] radv: rename radeon perfctr uconfig helpers To match other helpers. Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 2 +- src/amd/vulkan/radv_cs.h | 6 +++--- src/amd/vulkan/radv_perfcounter.c | 2 +- src/amd/vulkan/radv_spm.c | 10 +++++----- src/amd/vulkan/radv_sqtt.c | 14 +++++++------- 5 files changed, 17 insertions(+), 17 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 7088d70d60c..a7595e82217 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -12858,7 +12858,7 @@ radv_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstC radeon_emit(cs, 0); } else { /* The PKT3 CAM bit workaround seems needed for initializing this GDS register to zero. */ - radeon_set_uconfig_reg_perfctr(pdev->info.gfx_level, cmd_buffer->qf, cs, + radeon_set_uconfig_perfctr_reg(pdev->info.gfx_level, cmd_buffer->qf, cs, R_031088_GDS_STRMOUT_DWORDS_WRITTEN_0 + i * 4, 0); } } else { diff --git a/src/amd/vulkan/radv_cs.h b/src/amd/vulkan/radv_cs.h index 323d742b1ba..4c2f0669b15 100644 --- a/src/amd/vulkan/radv_cs.h +++ b/src/amd/vulkan/radv_cs.h @@ -109,7 +109,7 @@ radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) } static inline void -radeon_set_uconfig_reg_seq_perfctr(enum amd_gfx_level gfx_level, enum radv_queue_family qf, struct radeon_cmdbuf *cs, +radeon_set_uconfig_perfctr_reg_seq(enum amd_gfx_level gfx_level, enum radv_queue_family qf, struct radeon_cmdbuf *cs, unsigned reg, unsigned num) { /* @@ -124,10 +124,10 @@ radeon_set_uconfig_reg_seq_perfctr(enum amd_gfx_level gfx_level, enum radv_queue } static inline void -radeon_set_uconfig_reg_perfctr(enum amd_gfx_level gfx_level, enum radv_queue_family qf, struct radeon_cmdbuf *cs, +radeon_set_uconfig_perfctr_reg(enum amd_gfx_level gfx_level, enum radv_queue_family qf, struct radeon_cmdbuf *cs, unsigned reg, unsigned value) { - radeon_set_uconfig_reg_seq_perfctr(gfx_level, qf, cs, reg, 1); + radeon_set_uconfig_perfctr_reg_seq(gfx_level, qf, cs, reg, 1); radeon_emit(cs, value); } diff --git a/src/amd/vulkan/radv_perfcounter.c b/src/amd/vulkan/radv_perfcounter.c index 85e70a66715..816203745af 100644 --- a/src/amd/vulkan/radv_perfcounter.c +++ b/src/amd/vulkan/radv_perfcounter.c @@ -470,7 +470,7 @@ radv_emit_select(struct radv_cmd_buffer *cmd_buffer, struct ac_pc_block *block, return; for (idx = 0; idx < count; ++idx) { - radeon_set_uconfig_reg_perfctr(gfx_level, qf, cs, regs->select0[idx], + radeon_set_uconfig_perfctr_reg(gfx_level, qf, cs, regs->select0[idx], G_REG_SEL(selectors[idx]) | regs->select_or); } diff --git a/src/amd/vulkan/radv_spm.c b/src/amd/vulkan/radv_spm.c index 2236fa2eb42..f920f6d1daf 100644 --- a/src/amd/vulkan/radv_spm.c +++ b/src/amd/vulkan/radv_spm.c @@ -65,7 +65,7 @@ radv_emit_spm_counters(struct radv_device *device, struct radeon_cmdbuf *cs, enu const struct ac_spm_counter_select *cntr_sel = &spm->sq_wgp[instance].counters[b]; uint32_t reg_base = R_036700_SQ_PERFCOUNTER0_SELECT; - radeon_set_uconfig_reg_seq_perfctr(gfx_level, qf, cs, reg_base + b * 4, 1); + radeon_set_uconfig_perfctr_reg_seq(gfx_level, qf, cs, reg_base + b * 4, 1); radeon_emit(cs, cntr_sel->sel0); } } @@ -87,7 +87,7 @@ radv_emit_spm_counters(struct radv_device *device, struct radeon_cmdbuf *cs, enu const struct ac_spm_counter_select *cntr_sel = &spm->sqg[instance].counters[b]; uint32_t reg_base = R_036700_SQ_PERFCOUNTER0_SELECT; - radeon_set_uconfig_reg_seq_perfctr(gfx_level, qf, cs, reg_base + b * 4, 1); + radeon_set_uconfig_perfctr_reg_seq(gfx_level, qf, cs, reg_base + b * 4, 1); radeon_emit(cs, cntr_sel->sel0 | S_036700_SQC_BANK_MASK(0xf)); /* SQC_BANK_MASK only gfx10 */ } } @@ -109,10 +109,10 @@ radv_emit_spm_counters(struct radv_device *device, struct radeon_cmdbuf *cs, enu if (!cntr_sel->active) continue; - radeon_set_uconfig_reg_seq_perfctr(gfx_level, qf, cs, regs->select0[c], 1); + radeon_set_uconfig_perfctr_reg_seq(gfx_level, qf, cs, regs->select0[c], 1); radeon_emit(cs, cntr_sel->sel0); - radeon_set_uconfig_reg_seq_perfctr(gfx_level, qf, cs, regs->select1[c], 1); + radeon_set_uconfig_perfctr_reg_seq(gfx_level, qf, cs, regs->select1[c], 1); radeon_emit(cs, cntr_sel->sel1); } } @@ -205,7 +205,7 @@ radv_emit_spm_setup(struct radv_device *device, struct radeon_cmdbuf *cs, enum r uint32_t *data = (uint32_t *)spm->muxsel_lines[s][l].muxsel; /* Select MUXSEL_ADDR to point to the next muxsel. */ - radeon_set_uconfig_reg_perfctr(gfx_level, qf, cs, rlc_muxsel_addr, l * AC_SPM_MUXSEL_LINE_SIZE); + radeon_set_uconfig_perfctr_reg(gfx_level, qf, cs, rlc_muxsel_addr, l * AC_SPM_MUXSEL_LINE_SIZE); /* Write the muxsel line configuration with MUXSEL_DATA. */ radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + AC_SPM_MUXSEL_LINE_SIZE, 0)); diff --git a/src/amd/vulkan/radv_sqtt.c b/src/amd/vulkan/radv_sqtt.c index 537c7d8d66e..25f397c50b0 100644 --- a/src/amd/vulkan/radv_sqtt.c +++ b/src/amd/vulkan/radv_sqtt.c @@ -114,12 +114,12 @@ radv_emit_sqtt_start(const struct radv_device *device, struct radeon_cmdbuf *cs, if (pdev->info.gfx_level >= GFX11) { /* Order seems important for the following 2 registers. */ - radeon_set_uconfig_reg_perfctr(gfx_level, qf, cs, R_0367A4_SQ_THREAD_TRACE_BUF0_SIZE, + radeon_set_uconfig_perfctr_reg(gfx_level, qf, cs, R_0367A4_SQ_THREAD_TRACE_BUF0_SIZE, S_0367A4_SIZE(shifted_size) | S_0367A4_BASE_HI(shifted_va >> 32)); - radeon_set_uconfig_reg_perfctr(gfx_level, qf, cs, R_0367A0_SQ_THREAD_TRACE_BUF0_BASE, shifted_va); + radeon_set_uconfig_perfctr_reg(gfx_level, qf, cs, R_0367A0_SQ_THREAD_TRACE_BUF0_BASE, shifted_va); - radeon_set_uconfig_reg_perfctr(gfx_level, qf, cs, R_0367B4_SQ_THREAD_TRACE_MASK, + radeon_set_uconfig_perfctr_reg(gfx_level, qf, cs, R_0367B4_SQ_THREAD_TRACE_MASK, S_0367B4_WTYPE_INCLUDE(shader_mask) | S_0367B4_SA_SEL(0) | S_0367B4_WGP_SEL(active_cu / 2) | S_0367B4_SIMD_SEL(0)); @@ -138,10 +138,10 @@ radv_emit_sqtt_start(const struct radv_device *device, struct radeon_cmdbuf *cs, } sqtt_token_mask |= S_0367B8_TOKEN_EXCLUDE_GFX11(token_exclude) | S_0367B8_BOP_EVENTS_TOKEN_INCLUDE_GFX11(1); - radeon_set_uconfig_reg_perfctr(gfx_level, qf, cs, R_0367B8_SQ_THREAD_TRACE_TOKEN_MASK, sqtt_token_mask); + radeon_set_uconfig_perfctr_reg(gfx_level, qf, cs, R_0367B8_SQ_THREAD_TRACE_TOKEN_MASK, sqtt_token_mask); /* Should be emitted last (it enables thread traces). */ - radeon_set_uconfig_reg_perfctr(gfx_level, qf, cs, R_0367B0_SQ_THREAD_TRACE_CTRL, + radeon_set_uconfig_perfctr_reg(gfx_level, qf, cs, R_0367B0_SQ_THREAD_TRACE_CTRL, gfx11_get_sqtt_ctrl(device, true)); } else if (pdev->info.gfx_level >= GFX10) { @@ -364,7 +364,7 @@ radv_emit_sqtt_stop(const struct radv_device *device, struct radeon_cmdbuf *cs, radeon_emit(cs, 4); /* poll interval */ /* Disable the thread trace mode. */ - radeon_set_uconfig_reg_perfctr(gfx_level, qf, cs, R_0367B0_SQ_THREAD_TRACE_CTRL, + radeon_set_uconfig_perfctr_reg(gfx_level, qf, cs, R_0367B0_SQ_THREAD_TRACE_CTRL, gfx11_get_sqtt_ctrl(device, false)); /* Wait for thread trace completion. */ @@ -443,7 +443,7 @@ radv_emit_sqtt_userdata(const struct radv_cmd_buffer *cmd_buffer, const void *da /* Without the perfctr bit the CP might not always pass the * write on correctly. */ if (pdev->info.gfx_level >= GFX10) - radeon_set_uconfig_reg_seq_perfctr(gfx_level, qf, cs, R_030D08_SQ_THREAD_TRACE_USERDATA_2, count); + radeon_set_uconfig_perfctr_reg_seq(gfx_level, qf, cs, R_030D08_SQ_THREAD_TRACE_USERDATA_2, count); else radeon_set_uconfig_reg_seq(cs, R_030D08_SQ_THREAD_TRACE_USERDATA_2, count); radeon_emit_array(cs, dwords, count);