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nir: use nir_fsub_imm

Browse source 
Now that we have nir_fsub_imm, let's use it to save some typing!

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23179>
This commit is contained in:
Erik Faye-Lund 2023-05-08 09:54:46 +02:00 • committed by Marge Bot
parent 0ef104b057
commit c87e491107
12 changed files with 29 additions and 31 deletions
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2
src/broadcom/compiler/v3d_nir_lower_io.c
View file

@ -371,7 +371,7 @@ v3d_nir_lower_fragment_input(struct v3d_compile *c, nir_builder *b,
break;
}
if (c->fs_key->point_coord_upper_left && comp == 1)
result = nir_fsub(b, nir_imm_float(b, 1.0), result);
result = nir_fsub_imm(b, 1.0, result);
if (result != &intr->dest.ssa) {
nir_ssa_def_rewrite_uses_after(&intr->dest.ssa,
result,

2
src/compiler/nir/nir_lower_texcoord_replace.c
View file

@ -87,7 +87,7 @@ nir_lower_texcoord_replace_impl(nir_function_impl *impl,
nir_ssa_def *one = nir_imm_floatN_t(&b, 1.0, new_coord->bit_size);
nir_ssa_def *y = nir_channel(&b, new_coord, 1);
if (yinvert)
y = nir_fsub(&b, nir_imm_float(&b, 1.0), y);
y = nir_fsub_imm(&b, 1.0, y);
new_coord = nir_vec4(&b, nir_channel(&b, new_coord, 0),
y,
zero, one);

9
src/compiler/spirv/vtn_glsl450.c
View file

@ -400,7 +400,7 @@ handle_glsl450_alu(struct vtn_builder *b, enum GLSLstd450 entrypoint,
nir_ssa_def *cmp = nir_slt(nb, src[1], src[0]);
nb->exact = exact;
dest->def = nir_fsub(nb, nir_imm_floatN_t(nb, 1.0f, cmp->bit_size), cmp);
dest->def = nir_fsub_imm(nb, 1.0f, cmp);
break;
}
@ -567,10 +567,9 @@ handle_glsl450_alu(struct vtn_builder *b, enum GLSLstd450 entrypoint,
nir_fsqrt(nb, nir_ffma_imm2(nb, src[0], src[0], -1.0f))));
break;
case GLSLstd450Atanh: {
nir_ssa_def *one = nir_imm_floatN_t(nb, 1.0, src[0]->bit_size);
dest->def =
nir_fmul_imm(nb, nir_flog(nb, nir_fdiv(nb, nir_fadd_imm(nb, src[0], 1.0),
nir_fsub(nb, one, src[0]))),
nir_fsub_imm(nb, 1.0, src[0]))),
0.5f);
break;
}
@ -581,8 +580,8 @@ handle_glsl450_alu(struct vtn_builder *b, enum GLSLstd450 entrypoint,
case GLSLstd450Acos:
dest->def =
nir_fsub(nb, nir_imm_floatN_t(nb, M_PI_2f, src[0]->bit_size),
build_asin(nb, src[0], 0.08132463, -0.02363318, false));
nir_fsub_imm(nb, M_PI_2f,
build_asin(nb, src[0], 0.08132463, -0.02363318, false));
break;
case GLSLstd450Atan:

2
src/freedreno/ir3/ir3_nir_lower_tess.c
View file

@ -759,7 +759,7 @@ lower_tess_eval_block(nir_block *block, nir_builder *b, struct state *state)
nir_ssa_def *z;
if (state->topology == IR3_TESS_TRIANGLES)
z = nir_fsub(b, nir_fsub(b, nir_imm_float(b, 1.0f), y), x);
z = nir_fsub(b, nir_fsub_imm(b, 1.0f, y), x);
else
z = nir_imm_float(b, 0.0f);

2
src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp
View file

@ -668,7 +668,7 @@ r600_lower_tess_coord_impl(nir_builder *b, UNUSED nir_instr *instr, void *_optio
return nir_vec3(b,
tc_x,
tc_y,
nir_fsub(b, nir_imm_float(b, 1.0), nir_fadd(b, tc_x, tc_y)));
nir_fsub_imm(b, 1.0, nir_fadd(b, tc_x, tc_y)));
else
return nir_vec3(b, tc_x, tc_y, nir_imm_float(b, 0.0));
}

4
src/gallium/drivers/radeonsi/si_nir_lower_resource.c
View file

@ -91,7 +91,7 @@ static nir_ssa_def *load_ssbo_desc(nir_builder *b, nir_src *index,
nir_ssa_def *addr = ac_nir_load_arg(b, &s->args->ac, s->args->const_and_shader_buffers);
nir_ssa_def *slot = clamp_index(b, index->ssa, sel->info.base.num_ssbos);
slot = nir_isub(b, nir_imm_int(b, SI_NUM_SHADER_BUFFERS - 1), slot);
slot = nir_isub_imm(b, SI_NUM_SHADER_BUFFERS - 1, slot);
nir_ssa_def *offset = nir_ishl_imm(b, slot, 4);
return nir_load_smem_amd(b, 4, addr, offset);
@ -235,7 +235,7 @@ static nir_ssa_def *load_deref_image_desc(nir_builder *b, nir_deref_instr *deref
if (desc_type == AC_DESC_FMASK)
index = nir_iadd_imm(b, index, SI_NUM_IMAGES);
index = nir_isub(b, nir_imm_int(b, SI_NUM_IMAGE_SLOTS - 1), index);
index = nir_isub_imm(b, SI_NUM_IMAGE_SLOTS - 1, index);
nir_ssa_def *list = ac_nir_load_arg(b, &s->args->ac, s->args->samplers_and_images);
desc = load_image_desc(b, list, index, desc_type, !is_load, s);

2
src/gallium/drivers/v3d/v3d_blit.c
View file

@ -919,7 +919,7 @@ extract_unorm_2xrgb10a2_component_to_4xunorm16(nir_builder *b,
BITFIELD_MASK(30));
nir_ssa_def *finalword0 = nir_ushr(b, word0, shiftw0);
nir_ssa_def *word1 = nir_channel(b, value, 1);
nir_ssa_def *shiftw0tow1 = nir_isub(b, nir_imm_int(b, 30), shiftw0);
nir_ssa_def *shiftw0tow1 = nir_isub_imm(b, 30, shiftw0);
nir_ssa_def *word1toword0 = nir_ishl(b, word1, shiftw0tow1);
finalword0 = nir_ior(b, finalword0, word1toword0);
nir_ssa_def *finalword1 = nir_ushr(b, word1, shiftw0);

27
src/gallium/drivers/vc4/vc4_nir_lower_blend.c
View file

@ -83,9 +83,8 @@ vc4_blend_channel_f(nir_builder *b,
if (channel != 3) {
return nir_fmin(b,
src[3],
nir_fsub(b,
nir_imm_float(b, 1.0),
dst[3]));
nir_fsub_imm(b, 1.0,
dst[3]));
} else {
return nir_imm_float(b, 1.0);
}
@ -99,22 +98,22 @@ vc4_blend_channel_f(nir_builder *b,
case PIPE_BLENDFACTOR_ZERO:
return nir_imm_float(b, 0.0);
case PIPE_BLENDFACTOR_INV_SRC_COLOR:
return nir_fsub(b, nir_imm_float(b, 1.0), src[channel]);
return nir_fsub_imm(b, 1.0, src[channel]);
case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
return nir_fsub(b, nir_imm_float(b, 1.0), src[3]);
return nir_fsub_imm(b, 1.0, src[3]);
case PIPE_BLENDFACTOR_INV_DST_ALPHA:
return nir_fsub(b, nir_imm_float(b, 1.0), dst[3]);
return nir_fsub_imm(b, 1.0, dst[3]);
case PIPE_BLENDFACTOR_INV_DST_COLOR:
return nir_fsub(b, nir_imm_float(b, 1.0), dst[channel]);
return nir_fsub_imm(b, 1.0, dst[channel]);
case PIPE_BLENDFACTOR_INV_CONST_COLOR:
return nir_fsub(b, nir_imm_float(b, 1.0),
nir_load_system_value(b,
nir_intrinsic_load_blend_const_color_r_float +
channel,
0, 1, 32));
return nir_fsub_imm(b, 1.0,
nir_load_system_value(b,
nir_intrinsic_load_blend_const_color_r_float +
channel,
0, 1, 32));
case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
return nir_fsub(b, nir_imm_float(b, 1.0),
nir_load_blend_const_color_a_float(b));
return nir_fsub_imm(b, 1.0,
nir_load_blend_const_color_a_float(b));
default:
case PIPE_BLENDFACTOR_SRC1_COLOR:

2
src/gallium/drivers/vc4/vc4_nir_lower_io.c
View file

@ -260,7 +260,7 @@ vc4_nir_lower_fs_input(struct vc4_compile *c, nir_builder *b,
}
if (c->fs_key->point_coord_upper_left && comp == 1)
result = nir_fsub(b, nir_imm_float(b, 1.0), result);
result = nir_fsub_imm(b, 1.0, result);
if (result != &intr->dest.ssa) {
nir_ssa_def_rewrite_uses_after(&intr->dest.ssa,

2
src/gallium/drivers/zink/zink_compiler.c
View file

@ -3484,7 +3484,7 @@ invert_point_coord_instr(nir_builder *b, nir_instr *instr, void *data)
return false;
b->cursor = nir_after_instr(instr);
nir_ssa_def *def = nir_vec2(b, nir_channel(b, &intr->dest.ssa, 0),
nir_fsub(b, nir_imm_float(b, 1.0), nir_channel(b, &intr->dest.ssa, 1)));
nir_fsub_imm(b, 1.0, nir_channel(b, &intr->dest.ssa, 1)));
nir_ssa_def_rewrite_uses_after(&intr->dest.ssa, def, def->parent_instr);
return true;
}

4
src/mesa/main/ff_fragment_shader.c
View file

@ -473,7 +473,7 @@ emit_combine_source(struct texenv_fragment_program *p,
switch (operand) {
case TEXENV_OPR_ONE_MINUS_COLOR:
return nir_fsub(p->b, nir_imm_float(p->b, 1.0), src);
return nir_fsub_imm(p->b, 1.0, src);
case TEXENV_OPR_ALPHA:
return src->num_components == 1 ? src : nir_channel(p->b, src, 3);
@ -482,7 +482,7 @@ emit_combine_source(struct texenv_fragment_program *p,
nir_ssa_def *scalar =
src->num_components == 1 ? src : nir_channel(p->b, src, 3);
return nir_fsub(p->b, nir_imm_float(p->b, 1.0), scalar);
return nir_fsub_imm(p->b, 1.0, scalar);
}
case TEXENV_OPR_COLOR:

2
src/mesa/state_tracker/st_atifs_to_nir.c
View file

@ -205,7 +205,7 @@ prepare_argument(struct st_translate *t, const struct atifs_instruction *inst,
t->temps[MAX_NUM_FRAGMENT_REGISTERS_ATI + argId] = src;
if (srcReg->argMod & GL_COMP_BIT_ATI)
src = nir_fsub(t->b, nir_imm_vec4_float(t->b, 1.0), src);
src = nir_fsub_imm(t->b, 1.0, src);
if (srcReg->argMod & GL_BIAS_BIT_ATI)
src = nir_fadd_imm(t->b, src, -0.5);
if (srcReg->argMod & GL_2X_BIT_ATI)