mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-06 11:38:05 +02:00
nv50: Dehexify and bring up to date with new method defines.
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
This commit is contained in:
Marcin Kościelnicki
Francisco Jerez
parent
b46bcd8e7b
commit
c84cc09d41
8 changed files with 69 additions and 72 deletions
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@ -3498,7 +3498,7 @@ nv50_fragprog_validate(struct nv50_context *nv50)
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so_data (so, p->cfg.high_temp);
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so_method(so, tesla, NV50TCL_FP_RESULT_COUNT, 1);
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so_data (so, p->cfg.high_result);
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so_method(so, tesla, NV50TCL_FP_CTRL_UNK19A8, 1);
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so_method(so, tesla, NV50TCL_FP_CONTROL, 1);
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so_data (so, p->cfg.regs[2]);
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so_method(so, tesla, NV50TCL_FP_CTRL_UNK196C, 1);
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so_data (so, p->cfg.regs[3]);
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@ -3670,7 +3670,7 @@ nv50_linkage_validate(struct nv50_context *nv50)
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so_method(so, tesla, NV50TCL_FP_INTERPOLANT_CTRL, 1);
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so_data (so, reg[4]);
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so_method(so, tesla, 0x1540, 4);
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so_method(so, tesla, NV50TCL_NOPERSPECTIVE_BITMAP(0), 4);
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so_datap (so, lin, 4);
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if (nv50->rasterizer->pipe.point_sprite) {
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@ -77,9 +77,9 @@ nv50_query_begin(struct pipe_context *pipe, struct pipe_query *pq)
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struct nouveau_grobj *tesla = nv50->screen->tesla;
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struct nv50_query *q = nv50_query(pq);
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BEGIN_RING(chan, tesla, 0x1530, 1);
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BEGIN_RING(chan, tesla, NV50TCL_SAMPLECNT_RESET, 1);
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OUT_RING (chan, 1);
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BEGIN_RING(chan, tesla, 0x1514, 1);
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BEGIN_RING(chan, tesla, NV50TCL_SAMPLECNT_ENABLE, 1);
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OUT_RING (chan, 1);
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q->ready = FALSE;
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@ -231,8 +231,7 @@ nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
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break;
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case 0x80:
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case 0x90:
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/* this stupid name should be corrected. */
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tesla_class = NV54TCL;
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tesla_class = NV84TCL;
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break;
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case 0xa0:
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switch (chipset) {
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@ -242,7 +241,7 @@ nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
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tesla_class = NVA0TCL;
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break;
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default:
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tesla_class = 0x8597;
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tesla_class = NVA8TCL;
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break;
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}
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break;
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@ -287,7 +286,7 @@ nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
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so_data (so, chan->vram->handle);
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so_method(so, screen->eng2d, NV50_2D_OPERATION, 1);
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so_data (so, NV50_2D_OPERATION_SRCCOPY);
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so_method(so, screen->eng2d, 0x0290, 1);
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so_method(so, screen->eng2d, NV50_2D_CLIP_ENABLE, 1);
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so_data (so, 0);
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so_method(so, screen->eng2d, 0x0888, 1);
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so_data (so, 1);
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@ -297,34 +296,33 @@ nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
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/* Static tesla init */
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so = so_new(256, 20);
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so_method(so, screen->tesla, 0x1558, 1);
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so_data (so, 1);
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so_method(so, screen->tesla, NV50TCL_COND_MODE, 1);
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so_data (so, NV50TCL_COND_MODE_ALWAYS);
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so_method(so, screen->tesla, NV50TCL_DMA_NOTIFY, 1);
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so_data (so, screen->sync->handle);
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so_method(so, screen->tesla, NV50TCL_DMA_UNK0(0),
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NV50TCL_DMA_UNK0__SIZE);
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for (i = 0; i < NV50TCL_DMA_UNK0__SIZE; i++)
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so_method(so, screen->tesla, NV50TCL_DMA_ZETA, 11);
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for (i = 0; i < 11; i++)
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so_data(so, chan->vram->handle);
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so_method(so, screen->tesla, NV50TCL_DMA_UNK1(0),
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NV50TCL_DMA_UNK1__SIZE);
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for (i = 0; i < NV50TCL_DMA_UNK1__SIZE; i++)
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so_method(so, screen->tesla, NV50TCL_DMA_COLOR(0),
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NV50TCL_DMA_COLOR__SIZE);
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for (i = 0; i < NV50TCL_DMA_COLOR__SIZE; i++)
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so_data(so, chan->vram->handle);
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so_method(so, screen->tesla, 0x121c, 1);
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so_method(so, screen->tesla, NV50TCL_RT_CONTROL, 1);
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so_data (so, 1);
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/* activate all 32 lanes (threads) in a warp */
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so_method(so, screen->tesla, 0x19a0, 1);
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so_method(so, screen->tesla, NV50TCL_WARP_HALVES, 1);
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so_data (so, 0x2);
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so_method(so, screen->tesla, 0x1400, 1);
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so_data (so, 0xf);
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/* max TIC (bits 4:8) & TSC (ignored) bindings, per program type */
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so_method(so, screen->tesla, 0x13b4, 1);
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so_method(so, screen->tesla, NV50TCL_TEX_LIMITS(0), 1);
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so_data (so, 0x54);
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so_method(so, screen->tesla, 0x13bc, 1);
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so_method(so, screen->tesla, NV50TCL_TEX_LIMITS(2), 1);
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so_data (so, 0x54);
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/* origin is top left (set to 1 for bottom left) */
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so_method(so, screen->tesla, 0x13ac, 1);
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so_method(so, screen->tesla, NV50TCL_Y_ORIGIN_BOTTOM, 1);
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so_data (so, 0);
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so_method(so, screen->tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1);
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so_data (so, 8);
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@ -360,7 +358,7 @@ nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
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// B = buffer ID (maybe more than 1 byte)
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// N = CB index used in shader instruction
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// P = program type (0 = VP, 2 = GP, 3 = FP)
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so_method(so, screen->tesla, 0x1694, 1);
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so_method(so, screen->tesla, NV50TCL_SET_PROGRAM_CB, 1);
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so_data (so, 0x000BBNP1);
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*/
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@ -424,24 +422,24 @@ nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
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/* Vertex array limits - max them out */
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for (i = 0; i < 16; i++) {
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so_method(so, screen->tesla, NV50TCL_UNK1080_OFFSET_HIGH(i), 2);
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so_method(so, screen->tesla, NV50TCL_VERTEX_ARRAY_LIMIT_HIGH(i), 2);
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so_data (so, 0x000000ff);
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so_data (so, 0xffffffff);
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}
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so_method(so, screen->tesla, NV50TCL_DEPTH_RANGE_NEAR, 2);
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so_method(so, screen->tesla, NV50TCL_DEPTH_RANGE_NEAR(0), 2);
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so_data (so, fui(0.0));
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so_data (so, fui(1.0));
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/* no dynamic combination of TIC & TSC entries => only BIND_TIC used */
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so_method(so, screen->tesla, 0x1234, 1);
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so_method(so, screen->tesla, NV50TCL_LINKED_TSC, 1);
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so_data (so, 1);
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/* activate first scissor rectangle */
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so_method(so, screen->tesla, NV50TCL_SCISSOR_ENABLE, 1);
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so_method(so, screen->tesla, NV50TCL_SCISSOR_ENABLE(0), 1);
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so_data (so, 1);
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so_method(so, screen->tesla, 0x15e4, 1);
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so_method(so, screen->tesla, NV50TCL_EDGEFLAG_ENABLE, 1);
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so_data (so, 1); /* default edgeflag to TRUE */
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so_emit(chan, so);
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@ -295,7 +295,7 @@ nv50_rasterizer_state_create(struct pipe_context *pipe,
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so_method(so, tesla, NV50TCL_SHADE_MODEL, 1);
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so_data (so, cso->flatshade ? NV50TCL_SHADE_MODEL_FLAT :
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NV50TCL_SHADE_MODEL_SMOOTH);
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so_method(so, tesla, 0x1684, 1);
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so_method(so, tesla, NV50TCL_PROVOKING_VERTEX_LAST, 1);
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so_data (so, cso->flatshade_first ? 0 : 1);
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so_method(so, tesla, NV50TCL_VERTEX_TWO_SIDE_ENABLE, 1);
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@ -439,9 +439,8 @@ nv50_depth_stencil_alpha_state_create(struct pipe_context *pipe,
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so_data (so, 0);
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}
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/* XXX: keep hex values until header is updated (names reversed) */
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if (cso->stencil[0].enabled) {
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so_method(so, tesla, 0x1380, 8);
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so_method(so, tesla, NV50TCL_STENCIL_FRONT_ENABLE, 8);
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so_data (so, 1);
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so_data (so, nvgl_stencil_op(cso->stencil[0].fail_op));
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so_data (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
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@ -451,23 +450,23 @@ nv50_depth_stencil_alpha_state_create(struct pipe_context *pipe,
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so_data (so, cso->stencil[0].writemask);
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so_data (so, cso->stencil[0].valuemask);
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} else {
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so_method(so, tesla, 0x1380, 1);
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so_method(so, tesla, NV50TCL_STENCIL_FRONT_ENABLE, 1);
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so_data (so, 0);
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}
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if (cso->stencil[1].enabled) {
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so_method(so, tesla, 0x1594, 5);
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so_method(so, tesla, NV50TCL_STENCIL_BACK_ENABLE, 5);
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so_data (so, 1);
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so_data (so, nvgl_stencil_op(cso->stencil[1].fail_op));
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so_data (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
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so_data (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
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so_data (so, nvgl_comparison_op(cso->stencil[1].func));
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so_method(so, tesla, 0x0f54, 3);
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so_method(so, tesla, NV50TCL_STENCIL_BACK_FUNC_REF, 3);
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so_data (so, cso->stencil[1].ref_value);
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so_data (so, cso->stencil[1].writemask);
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so_data (so, cso->stencil[1].valuemask);
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} else {
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so_method(so, tesla, 0x1594, 1);
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so_method(so, tesla, NV50TCL_STENCIL_BACK_ENABLE, 1);
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so_data (so, 0);
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}
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@ -41,7 +41,7 @@ nv50_state_validate_fb(struct nv50_context *nv50)
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* FP result 0 always goes to RT[0], bits 4 - 6 are ignored.
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* Ambiguous assignment results in no rendering (no DATA_ERROR).
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*/
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so_method(so, tesla, 0x121c, 1);
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so_method(so, tesla, NV50TCL_RT_CONTROL, 1);
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so_data (so, fb->nr_cbufs |
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(0 << 4) | (1 << 7) | (2 << 10) | (3 << 13) |
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(4 << 16) | (5 << 19) | (6 << 22) | (7 << 25));
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@ -87,7 +87,7 @@ nv50_state_validate_fb(struct nv50_context *nv50)
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level[fb->cbufs[i]->level].tile_mode << 4);
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so_data(so, 0x00000000);
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so_method(so, tesla, 0x1224, 1);
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so_method(so, tesla, NV50TCL_RT_ARRAY_MODE, 1);
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so_data (so, 1);
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}
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@ -124,22 +124,22 @@ nv50_state_validate_fb(struct nv50_context *nv50)
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level[fb->zsbuf->level].tile_mode << 4);
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so_data(so, 0x00000000);
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so_method(so, tesla, 0x1538, 1);
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so_method(so, tesla, NV50TCL_ZETA_ENABLE, 1);
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so_data (so, 1);
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so_method(so, tesla, NV50TCL_ZETA_HORIZ, 3);
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so_data (so, fb->zsbuf->width);
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so_data (so, fb->zsbuf->height);
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so_data (so, 0x00010001);
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} else {
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so_method(so, tesla, 0x1538, 1);
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so_method(so, tesla, NV50TCL_ZETA_ENABLE, 1);
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so_data (so, 0);
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}
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so_method(so, tesla, NV50TCL_VIEWPORT_HORIZ, 2);
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so_method(so, tesla, NV50TCL_VIEWPORT_HORIZ(0), 2);
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so_data (so, w << 16);
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so_data (so, h << 16);
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/* set window lower left corner */
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so_method(so, tesla, NV50TCL_WINDOW_LEFT, 2);
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so_method(so, tesla, NV50TCL_WINDOW_OFFSET_X, 2);
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so_data (so, 0);
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so_data (so, 0);
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/* set screen scissor rectangle */
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@ -325,7 +325,7 @@ nv50_state_validate(struct nv50_context *nv50)
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nv50->state.scissor_enabled = rast->scissor;
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so = so_new(3, 0);
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so_method(so, tesla, NV50TCL_SCISSOR_HORIZ, 2);
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so_method(so, tesla, NV50TCL_SCISSOR_HORIZ(0), 2);
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if (nv50->state.scissor_enabled) {
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so_data(so, (s->maxx << 16) | s->minx);
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so_data(so, (s->maxy << 16) | s->miny);
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@ -355,11 +355,11 @@ scissor_uptodate:
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so = so_new(14, 0);
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if (!bypass) {
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so_method(so, tesla, NV50TCL_VIEWPORT_TRANSLATE(0), 3);
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so_method(so, tesla, NV50TCL_VIEWPORT_TRANSLATE_X(0), 3);
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so_data (so, fui(nv50->viewport.translate[0]));
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so_data (so, fui(nv50->viewport.translate[1]));
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so_data (so, fui(nv50->viewport.translate[2]));
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so_method(so, tesla, NV50TCL_VIEWPORT_SCALE(0), 3);
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so_method(so, tesla, NV50TCL_VIEWPORT_SCALE_X(0), 3);
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so_data (so, fui(nv50->viewport.scale[0]));
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so_data (so, fui(nv50->viewport.scale[1]));
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so_data (so, fui(nv50->viewport.scale[2]));
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@ -440,7 +440,7 @@ void nv50_so_init_sifc(struct nv50_context *nv50,
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so_data (so, 1);
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so_reloc (so, bo, offset, reloc | NOUVEAU_BO_HIGH, 0, 0);
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so_reloc (so, bo, offset, reloc | NOUVEAU_BO_LOW, 0, 0);
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so_method(so, eng2d, NV50_2D_SIFC_UNK0800, 2);
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so_method(so, eng2d, NV50_2D_SIFC_BITMAP_ENABLE, 2);
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so_data (so, 0);
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so_data (so, NV50_2D_SIFC_FORMAT_R8_UNORM);
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so_method(so, eng2d, NV50_2D_SIFC_WIDTH, 10);
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@ -176,11 +176,11 @@ nv50_surface_fill(struct pipe_context *pipe, struct pipe_surface *dest,
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if (ret)
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return;
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BEGIN_RING(chan, eng2d, 0x0580, 3);
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OUT_RING (chan, 4);
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BEGIN_RING(chan, eng2d, NV50_2D_DRAW_SHAPE, 3);
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OUT_RING (chan, NV50_2D_DRAW_SHAPE_RECTANGLES);
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OUT_RING (chan, format);
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OUT_RING (chan, value);
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BEGIN_RING(chan, eng2d, NV50_2D_RECT_X1, 4);
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BEGIN_RING(chan, eng2d, NV50_2D_DRAW_POINT32_X(0), 4);
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OUT_RING (chan, destx);
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OUT_RING (chan, desty);
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OUT_RING (chan, width);
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@ -47,7 +47,7 @@ nv50_transfer_rect_m2mf(struct pipe_screen *pscreen,
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NV50_MEMORY_TO_MEMORY_FORMAT_LINEAR_IN, 1);
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OUT_RING (chan, 1);
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BEGIN_RING(chan, m2mf,
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NV50_MEMORY_TO_MEMORY_FORMAT_PITCH_IN, 1);
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NV04_MEMORY_TO_MEMORY_FORMAT_PITCH_IN, 1);
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OUT_RING (chan, src_pitch);
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src_offset += (sy * src_pitch) + (sx * cpp);
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} else {
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@ -66,7 +66,7 @@ nv50_transfer_rect_m2mf(struct pipe_screen *pscreen,
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NV50_MEMORY_TO_MEMORY_FORMAT_LINEAR_OUT, 1);
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OUT_RING (chan, 1);
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BEGIN_RING(chan, m2mf,
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NV50_MEMORY_TO_MEMORY_FORMAT_PITCH_OUT, 1);
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NV04_MEMORY_TO_MEMORY_FORMAT_PITCH_OUT, 1);
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OUT_RING (chan, dst_pitch);
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dst_offset += (dy * dst_pitch) + (dx * cpp);
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} else {
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@ -89,7 +89,7 @@ nv50_transfer_rect_m2mf(struct pipe_screen *pscreen,
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OUT_RELOCh(chan, src_bo, src_offset, src_reloc);
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OUT_RELOCh(chan, dst_bo, dst_offset, dst_reloc);
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BEGIN_RING(chan, m2mf,
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NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 2);
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NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 2);
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OUT_RELOCl(chan, src_bo, src_offset, src_reloc);
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OUT_RELOCl(chan, dst_bo, dst_offset, dst_reloc);
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if (src_bo->tile_flags) {
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@ -107,7 +107,7 @@ nv50_transfer_rect_m2mf(struct pipe_screen *pscreen,
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dst_offset += (line_count * dst_pitch);
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}
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BEGIN_RING(chan, m2mf,
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NV50_MEMORY_TO_MEMORY_FORMAT_LINE_LENGTH_IN, 4);
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NV04_MEMORY_TO_MEMORY_FORMAT_LINE_LENGTH_IN, 4);
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OUT_RING (chan, width * cpp);
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OUT_RING (chan, line_count);
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OUT_RING (chan, 0x00000101);
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@ -291,7 +291,7 @@ nv50_upload_sifc(struct nv50_context *nv50,
|
|||
|
||||
/* NV50_2D_OPERATION_SRCCOPY assumed already set */
|
||||
|
||||
BEGIN_RING(chan, eng2d, NV50_2D_SIFC_UNK0800, 2);
|
||||
BEGIN_RING(chan, eng2d, NV50_2D_SIFC_BITMAP_ENABLE, 2);
|
||||
OUT_RING (chan, 0);
|
||||
OUT_RING (chan, src_format);
|
||||
BEGIN_RING(chan, eng2d, NV50_2D_SIFC_WIDTH, 10);
|
||||
|
|
@ -334,6 +334,6 @@ nv50_upload_sifc(struct nv50_context *nv50,
|
|||
src += src_pitch;
|
||||
}
|
||||
|
||||
BEGIN_RING(chan, tesla, 0x1440, 1);
|
||||
BEGIN_RING(chan, tesla, NV50TCL_CODE_CB_FLUSH, 1);
|
||||
OUT_RING (chan, 0);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -99,19 +99,19 @@ nv50_vbo_size_to_hw(unsigned size, unsigned nr_c)
|
|||
{
|
||||
static const uint32_t hw_values[] = {
|
||||
0, 0, 0, 0,
|
||||
NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_8,
|
||||
NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_8_8,
|
||||
NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_8_8_8,
|
||||
NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_8_8_8_8,
|
||||
NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_16,
|
||||
NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_16_16,
|
||||
NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_16_16_16,
|
||||
NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_16_16_16_16,
|
||||
NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8,
|
||||
NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8_8,
|
||||
NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8_8_8,
|
||||
NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8_8_8_8,
|
||||
NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16,
|
||||
NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16_16,
|
||||
NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16_16_16,
|
||||
NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16_16_16_16,
|
||||
0, 0, 0, 0,
|
||||
NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_32,
|
||||
NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_32_32,
|
||||
NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_32_32_32,
|
||||
NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_32_32_32_32 };
|
||||
NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32,
|
||||
NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32_32,
|
||||
NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32,
|
||||
NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32 };
|
||||
|
||||
/* we'd also have R11G11B10 and R10G10B10A2 */
|
||||
|
||||
|
|
@ -198,7 +198,7 @@ nv50_draw_elements_inline_u08(struct nv50_context *nv50, uint8_t *map,
|
|||
return nv50_push_elements_u08(nv50, map, count);
|
||||
|
||||
if (count & 1) {
|
||||
BEGIN_RING(chan, tesla, 0x15e8, 1);
|
||||
BEGIN_RING(chan, tesla, NV50TCL_VB_ELEMENT_U32, 1);
|
||||
OUT_RING (chan, map[0]);
|
||||
map++;
|
||||
count--;
|
||||
|
|
@ -208,7 +208,7 @@ nv50_draw_elements_inline_u08(struct nv50_context *nv50, uint8_t *map,
|
|||
unsigned nr = count > 2046 ? 2046 : count;
|
||||
int i;
|
||||
|
||||
BEGIN_RING(chan, tesla, 0x400015f0, nr >> 1);
|
||||
BEGIN_RING(chan, tesla, NV50TCL_VB_ELEMENT_U16 | 0x40000000, nr >> 1);
|
||||
for (i = 0; i < nr; i += 2)
|
||||
OUT_RING (chan, (map[i + 1] << 16) | map[i]);
|
||||
|
||||
|
|
@ -231,7 +231,7 @@ nv50_draw_elements_inline_u16(struct nv50_context *nv50, uint16_t *map,
|
|||
return nv50_push_elements_u16(nv50, map, count);
|
||||
|
||||
if (count & 1) {
|
||||
BEGIN_RING(chan, tesla, 0x15e8, 1);
|
||||
BEGIN_RING(chan, tesla, NV50TCL_VB_ELEMENT_U32, 1);
|
||||
OUT_RING (chan, map[0]);
|
||||
map++;
|
||||
count--;
|
||||
|
|
@ -241,7 +241,7 @@ nv50_draw_elements_inline_u16(struct nv50_context *nv50, uint16_t *map,
|
|||
unsigned nr = count > 2046 ? 2046 : count;
|
||||
int i;
|
||||
|
||||
BEGIN_RING(chan, tesla, 0x400015f0, nr >> 1);
|
||||
BEGIN_RING(chan, tesla, NV50TCL_VB_ELEMENT_U16 | 0x40000000, nr >> 1);
|
||||
for (i = 0; i < nr; i += 2)
|
||||
OUT_RING (chan, (map[i + 1] << 16) | map[i]);
|
||||
|
||||
|
|
@ -266,7 +266,7 @@ nv50_draw_elements_inline_u32(struct nv50_context *nv50, uint32_t *map,
|
|||
while (count) {
|
||||
unsigned nr = count > 2047 ? 2047 : count;
|
||||
|
||||
BEGIN_RING(chan, tesla, 0x400015e8, nr);
|
||||
BEGIN_RING(chan, tesla, NV50TCL_VB_ELEMENT_U32 | 0x40000000, nr);
|
||||
OUT_RINGp (chan, map, nr);
|
||||
|
||||
count -= nr;
|
||||
|
|
@ -373,7 +373,7 @@ nv50_vbo_static_attrib(struct nv50_context *nv50, unsigned attrib,
|
|||
break;
|
||||
case 1:
|
||||
if (attrib == nv50->vertprog->cfg.edgeflag_in) {
|
||||
so_method(so, tesla, 0x15e4, 1);
|
||||
so_method(so, tesla, NV50TCL_EDGEFLAG_ENABLE, 1);
|
||||
so_data (so, v[0] ? 1 : 0);
|
||||
}
|
||||
so_method(so, tesla, NV50TCL_VTX_ATTR_1F(attrib), 1);
|
||||
|
|
@ -452,7 +452,7 @@ nv50_vbo_validate(struct nv50_context *nv50)
|
|||
NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0);
|
||||
|
||||
/* vertex array limits */
|
||||
so_method(vtxbuf, tesla, 0x1080 + (i * 8), 2);
|
||||
so_method(vtxbuf, tesla, NV50TCL_VERTEX_ARRAY_LIMIT_HIGH(i), 2);
|
||||
so_reloc (vtxbuf, bo, vb->buffer->size - 1,
|
||||
NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD |
|
||||
NOUVEAU_BO_HIGH, 0, 0);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue