diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h
index 7c0d1d0e757..65c9f8fe4f9 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -1559,13 +1559,11 @@ enum ENUM_PACKED brw_rnd_mode {
 #define GEN_RT_BTD_SHADER_TYPE_MISS           2
 #define GEN_RT_BTD_SHADER_TYPE_INTERSECTION   3
 
-/* Starting with Xe-HPG, the old dataport was massively reworked dataport.
+/* Starting with Xe-HPG, the old dataport was massively reworked.
  * The new thing, called Load/Store Cache or LSC, has a significantly improved
  * interface.  Instead of bespoke messages for every case, there's basically
  * one or two messages with different bits to control things like address
- * size, how much data is read/written, etc.  It's way nicer but also means we
- * get to rewrite all our dataport encoding/decoding code.  This patch kicks
- * off the party with all of the new enums.
+ * size, how much data is read/written, etc.
  */
 enum lsc_opcode {
    LSC_OP_LOAD            = 0,