diff --git a/.pick_status.json b/.pick_status.json index 22d3ea150f9..416b09f09e9 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -284,7 +284,7 @@ "description": "radv: add radv_disable_hiz_his_gfx12 and enable for Mafia Definitive Edition", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": null, "notes": null diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 7efe973940c..49eaea2fbd9 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -6945,7 +6945,6 @@ radv_BeginCommandBuffer(VkCommandBuffer commandBuffer, const VkCommandBufferBegi if (resume_info) { radv_CmdBeginRendering(commandBuffer, resume_info); } else { - const struct radv_instance *instance = radv_physical_device_instance(pdev); const VkCommandBufferInheritanceRenderingInfo *inheritance_info = vk_get_command_buffer_inheritance_rendering_info(cmd_buffer->vk.level, pBeginInfo); @@ -6974,7 +6973,7 @@ radv_BeginCommandBuffer(VkCommandBuffer commandBuffer, const VkCommandBufferBegi if (vk_format_has_stencil(render->ds_att.format)) render->ds_att_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT; - if (pdev->info.gfx_level >= GFX12 && render->ds_att.format && !(instance->debug_flags & RADV_DEBUG_NO_HIZ)) { + if (pdev->info.gfx_level >= GFX12 && pdev->use_hiz && render->ds_att.format) { /* For inherited rendering with secondary commands buffers, assume HiZ/HiS is enabled if * there is a depth/stencil attachment. This is required to apply hardware workarounds * on GFX12. diff --git a/src/amd/vulkan/radv_dgc.c b/src/amd/vulkan/radv_dgc.c index 5ddb8a9545a..e8d457b3b60 100644 --- a/src/amd/vulkan/radv_dgc.c +++ b/src/amd/vulkan/radv_dgc.c @@ -205,7 +205,6 @@ radv_get_sequence_size_graphics(const struct radv_indirect_command_layout *layou { const struct radv_device *device = container_of(layout->vk.base.device, struct radv_device, vk); const struct radv_physical_device *pdev = radv_device_physical(device); - const struct radv_instance *instance = radv_physical_device_instance(pdev); const VkGeneratedCommandsPipelineInfoEXT *pipeline_info = vk_find_struct_const(pNext, GENERATED_COMMANDS_PIPELINE_INFO_EXT); @@ -287,7 +286,7 @@ radv_get_sequence_size_graphics(const struct radv_indirect_command_layout *layou } } - if (pdev->info.gfx_level == GFX12 && !(instance->debug_flags & RADV_DEBUG_NO_HIZ)) { + if (pdev->info.gfx_level == GFX12 && pdev->use_hiz) { /* HiZ/HiS hw workaround */ *cmd_size += 8 * 4; } @@ -1140,9 +1139,8 @@ dgc_gfx12_emit_hiz_his_wa(struct dgc_cmdbuf *cs) { const struct radv_device *device = cs->dev; const struct radv_physical_device *pdev = radv_device_physical(device); - const struct radv_instance *instance = radv_physical_device_instance(pdev); - if (pdev->info.gfx_level == GFX12 && !(instance->debug_flags & RADV_DEBUG_NO_HIZ)) { + if (pdev->info.gfx_level == GFX12 && pdev->use_hiz) { dgc_cs_begin(cs); dgc_cs_emit_imm(PKT3(PKT3_RELEASE_MEM, 6, 0)); dgc_cs_emit_imm(S_490_EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | S_490_EVENT_INDEX(5)); diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c index 28755aeae8d..4debc408f73 100644 --- a/src/amd/vulkan/radv_formats.c +++ b/src/amd/vulkan/radv_formats.c @@ -1255,9 +1255,8 @@ radv_GetPhysicalDeviceImageFormatProperties2(VkPhysicalDevice physicalDevice, image_compression_props->imageCompressionFixedRateFlags = VK_IMAGE_COMPRESSION_FIXED_RATE_NONE_EXT; if (vk_format_is_depth_or_stencil(format)) { - image_compression_props->imageCompressionFlags = (instance->debug_flags & RADV_DEBUG_NO_HIZ) - ? VK_IMAGE_COMPRESSION_DISABLED_EXT - : VK_IMAGE_COMPRESSION_DEFAULT_EXT; + image_compression_props->imageCompressionFlags = + pdev->use_hiz ? VK_IMAGE_COMPRESSION_DEFAULT_EXT : VK_IMAGE_COMPRESSION_DISABLED_EXT; } else { image_compression_props->imageCompressionFlags = ((instance->debug_flags & RADV_DEBUG_NO_DCC) || pdev->info.gfx_level < GFX8) diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 2aa76dfc5f4..4b9f656fa26 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -381,11 +381,12 @@ radv_use_htile_for_image(const struct radv_device *device, const struct radv_ima const struct radv_instance *instance = radv_physical_device_instance(pdev); const enum amd_gfx_level gfx_level = pdev->info.gfx_level; + if (!pdev->use_hiz) + return false; + const VkImageCompressionControlEXT *compression = vk_find_struct_const(pCreateInfo->pNext, IMAGE_COMPRESSION_CONTROL_EXT); - - if (instance->debug_flags & RADV_DEBUG_NO_HIZ || - (compression && compression->flags == VK_IMAGE_COMPRESSION_DISABLED_EXT)) + if (compression && compression->flags == VK_IMAGE_COMPRESSION_DISABLED_EXT) return false; if (image->vk.usage & VK_IMAGE_USAGE_STORAGE_BIT) diff --git a/src/amd/vulkan/radv_instance.c b/src/amd/vulkan/radv_instance.c index ef3d1938682..eea1680433d 100644 --- a/src/amd/vulkan/radv_instance.c +++ b/src/amd/vulkan/radv_instance.c @@ -193,6 +193,7 @@ static const driOptionDescription radv_dri_options[] = { DRI_CONF_RADV_LOWER_TERMINATE_TO_DISCARD(false) DRI_CONF_RADV_APP_LAYER() DRI_CONF_RADV_FORCE_64K_SPARSE_ALIGNMENT(false) + DRI_CONF_RADV_DISABLE_HIZ_HIS_GFX12(false) DRI_CONF_SECTION_END }; // clang-format on @@ -291,6 +292,8 @@ radv_init_dri_options(struct radv_instance *instance) driQueryOptionb(&instance->drirc.options, "radv_lower_terminate_to_discard"); instance->drirc.force_64k_sparse_alignment = driQueryOptionb(&instance->drirc.options, "radv_force_64k_sparse_alignment"); + + instance->drirc.disable_hiz_his_gfx12 = driQueryOptionb(&instance->drirc.options, "radv_disable_hiz_his_gfx12"); } static const struct vk_instance_extension_table radv_instance_extensions_supported = { diff --git a/src/amd/vulkan/radv_instance.h b/src/amd/vulkan/radv_instance.h index 3688812816c..274336b0432 100644 --- a/src/amd/vulkan/radv_instance.h +++ b/src/amd/vulkan/radv_instance.h @@ -75,6 +75,7 @@ struct radv_instance { bool disable_dcc_stores; bool lower_terminate_to_discard; bool force_64k_sparse_alignment; + bool disable_hiz_his_gfx12; char *app_layer; uint8_t override_graphics_shader_version; uint8_t override_compute_shader_version; diff --git a/src/amd/vulkan/radv_physical_device.c b/src/amd/vulkan/radv_physical_device.c index be6cb596061..0c8e51de27f 100644 --- a/src/amd/vulkan/radv_physical_device.c +++ b/src/amd/vulkan/radv_physical_device.c @@ -89,8 +89,7 @@ radv_transfer_queue_enabled(const struct radv_physical_device *pdev) static bool radv_vrs_attachment_enabled(const struct radv_physical_device *pdev) { - const struct radv_instance *instance = radv_physical_device_instance(pdev); - return pdev->info.gfx_level >= GFX11 || !(instance->debug_flags & RADV_DEBUG_NO_HIZ); + return pdev->info.gfx_level >= GFX11 || pdev->use_hiz; } static bool @@ -2131,6 +2130,10 @@ radv_physical_device_try_create(struct radv_instance *instance, drmDevicePtr drm pdev->use_fmask = pdev->info.gfx_level < GFX11 && !(instance->debug_flags & RADV_DEBUG_NO_FMASK); + pdev->use_hiz = !(instance->debug_flags & RADV_DEBUG_NO_HIZ); + if (pdev->info.gfx_level == GFX12 && instance->drirc.disable_hiz_his_gfx12) + pdev->use_hiz = false; + pdev->use_ngg = (pdev->info.gfx_level >= GFX10 && pdev->info.family != CHIP_NAVI14 && !(instance->debug_flags & RADV_DEBUG_NO_NGG)) || pdev->info.gfx_level >= GFX11; diff --git a/src/amd/vulkan/radv_physical_device.h b/src/amd/vulkan/radv_physical_device.h index c599357549e..be6207360d4 100644 --- a/src/amd/vulkan/radv_physical_device.h +++ b/src/amd/vulkan/radv_physical_device.h @@ -95,6 +95,9 @@ struct radv_physical_device { /* Whether to enable FMASK compression for MSAA textures (GFX6-GFX10.3) */ bool use_fmask; + /* Whether to enable HTILE compression for depth/stencil images. */ + bool use_hiz; + /* Whether to enable NGG. */ bool use_ngg; diff --git a/src/util/00-radv-defaults.conf b/src/util/00-radv-defaults.conf index 17e4e0e6392..8f89496ee53 100644 --- a/src/util/00-radv-defaults.conf +++ b/src/util/00-radv-defaults.conf @@ -186,6 +186,10 @@ Application bugs worked around in this file: