From c8226d37829051b949913867e21341f4707321e9 Mon Sep 17 00:00:00 2001 From: Bas Nieuwenhuizen Date: Fri, 2 Jun 2017 23:51:50 +0200 Subject: [PATCH] radv: Set both compute and graphics SGPRS on descriptor set flush. We clear the descriptors_dirty array afterwards, so the SGPRs for the other pipeline don't get updated on the flush for that other draw/dispatch, so we have to make sure we do it immediately. Signed-off-by: Bas Nieuwenhuizen Reviewed-by: Dave Airlie Fixes: ae61ddabe8c "radv: move userdata sgpr ownership to compiler side." (cherry picked from commit 5fb8bb306534d633ceb4e33d89984718326773ba) [Emil Velikov: drop radv_flush_indirect_descriptor_sets hunk - missing in branch] Signed-off-by: Emil Velikov Conflicts: src/amd/vulkan/radv_cmd_buffer.c --- src/amd/vulkan/radv_cmd_buffer.c | 56 +++++++++++++++----------------- 1 file changed, 27 insertions(+), 29 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index bd1541691a2..efeb34c4723 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1268,38 +1268,39 @@ emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer, static void radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer, - struct radv_pipeline *pipeline, VkShaderStageFlags stages, struct radv_descriptor_set *set, unsigned idx) { - if (stages & VK_SHADER_STAGE_FRAGMENT_BIT) - emit_stage_descriptor_set_userdata(cmd_buffer, pipeline, - idx, set->va, - MESA_SHADER_FRAGMENT); + if (cmd_buffer->state.pipeline) { + if (stages & VK_SHADER_STAGE_FRAGMENT_BIT) + emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline, + idx, set->va, + MESA_SHADER_FRAGMENT); - if (stages & VK_SHADER_STAGE_VERTEX_BIT) - emit_stage_descriptor_set_userdata(cmd_buffer, pipeline, - idx, set->va, - MESA_SHADER_VERTEX); + if (stages & VK_SHADER_STAGE_VERTEX_BIT) + emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline, + idx, set->va, + MESA_SHADER_VERTEX); - if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline)) - emit_stage_descriptor_set_userdata(cmd_buffer, pipeline, - idx, set->va, - MESA_SHADER_GEOMETRY); + if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(cmd_buffer->state.pipeline)) + emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline, + idx, set->va, + MESA_SHADER_GEOMETRY); - if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(pipeline)) - emit_stage_descriptor_set_userdata(cmd_buffer, pipeline, - idx, set->va, - MESA_SHADER_TESS_CTRL); + if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(cmd_buffer->state.pipeline)) + emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline, + idx, set->va, + MESA_SHADER_TESS_CTRL); - if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(pipeline)) - emit_stage_descriptor_set_userdata(cmd_buffer, pipeline, - idx, set->va, - MESA_SHADER_TESS_EVAL); + if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(cmd_buffer->state.pipeline)) + emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline, + idx, set->va, + MESA_SHADER_TESS_EVAL); + } - if (stages & VK_SHADER_STAGE_COMPUTE_BIT) - emit_stage_descriptor_set_userdata(cmd_buffer, pipeline, + if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT)) + emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline, idx, set->va, MESA_SHADER_COMPUTE); } @@ -1324,7 +1325,6 @@ radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer) static void radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer, - struct radv_pipeline *pipeline, VkShaderStageFlags stages) { unsigned i; @@ -1345,7 +1345,7 @@ radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer, if (!set) continue; - radv_emit_descriptor_set_userdata(cmd_buffer, pipeline, stages, set, i); + radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i); } cmd_buffer->state.descriptors_dirty = 0; cmd_buffer->state.push_descriptors_dirty = false; @@ -1515,8 +1515,7 @@ radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer, radv_emit_primitive_reset_state(cmd_buffer, indexed_draw); - radv_flush_descriptors(cmd_buffer, cmd_buffer->state.pipeline, - VK_SHADER_STAGE_ALL_GRAPHICS); + radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS); radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline, VK_SHADER_STAGE_ALL_GRAPHICS); @@ -2757,8 +2756,7 @@ static void radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer) { radv_emit_compute_pipeline(cmd_buffer); - radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline, - VK_SHADER_STAGE_COMPUTE_BIT); + radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT); radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline, VK_SHADER_STAGE_COMPUTE_BIT); si_emit_cache_flush(cmd_buffer);