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r600/sfn: Use a heuristic to keep SSBO setup and store close
When SSBO instructions use constant address values the address loading
is immediately ready, scheduling the address loads early increases
the register pressure, so force a new instruction block to work around
this problem.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6975
Fixes: 79ca456b48
r600/sfn: rewrite NIR backend
v2: do handling in shader block to be thread save (hinted to by Filip)
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
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4 changed files with 6 additions and 7 deletions
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@ -210,6 +210,8 @@ public:
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bool kcache_reservation_failed() const { return m_kcache_alloc_failed;}
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int inc_rat_emitted() { return ++m_emitted_rat_instr;}
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static void set_chipclass(r600_chip_class chip_class);
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private:
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@ -234,6 +236,7 @@ private:
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int m_lds_group_requirement{0};
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AluInstr *m_lds_group_start{nullptr};
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static unsigned s_max_kcache_banks;
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int m_emitted_rat_instr{0};
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};
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class InstrWithVectorResult : public Instr {
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@ -559,12 +559,6 @@ bool RatInstr::emit_ssbo_load(nir_intrinsic_instr *intr, Shader& shader)
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bool RatInstr::emit_ssbo_store(nir_intrinsic_instr *instr, Shader& shader)
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{
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/* Forche the scheduler to not move the preparation too far away, by starting
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* a new block (TODO: better priority handling in the scheduler)*/
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if (nir_src_num_components(instr->src[0]) > 2)
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shader.start_new_block(0);
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auto &vf = shader.value_factory();
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auto orig_addr = vf.src(instr->src[2], 0);
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@ -194,7 +194,6 @@ private:
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int m_element_size{3};
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bool m_need_ack{false};
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bool m_need_mark{false};
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};
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@ -1085,6 +1085,9 @@ void Shader::InstructionChain::visit(RatInstr *instr)
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if (prepare_mem_barrier)
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instr->set_ack();
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if (this_shader->m_current_block->inc_rat_emitted() > 15)
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this_shader->start_new_block(0);
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}
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void Shader::InstructionChain::apply(Instr *current, Instr **last) {
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