From c7e678b302ca332790f447fc46f9a40eb989a165 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Fri, 21 Apr 2023 10:11:36 +0200 Subject: [PATCH] radv/amdgpu: fix adding continue preambles and postambles BOs to the list Previously, continue preambles and postambles were added directly to the CS array which means all BOs were correctly added to the BO list, and this has been broken recently. IB BOs need to be added to the list. When a BO isn't added to the list as part of a submission, it might randomly VM faults. This fixes VM faults and random GPU hangs on NAVI21 in Mesa CI. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8849 Fixes: 41a9bced313 ("radv: Fill continue preambles and postambles properly.") Signed-off-by: Samuel Pitoiset Part-of: (cherry picked from commit 84d8ea6e2b481524491c85bb9bf996e1056ccc70) --- .pick_status.json | 2 +- src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 19 ++++++++++++++++--- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 120ad474242..5f059794062 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -283,7 +283,7 @@ "description": "radv/amdgpu: fix adding continue preambles and postambles BOs to the list", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": "41a9bced313dded77693e9df10e5ccb18542320f" }, diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c index 7107fc0b896..924dfaffc7b 100644 --- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c +++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c @@ -875,12 +875,24 @@ radv_amdgpu_winsys_cs_submit_internal( struct radv_amdgpu_cs *last_cs = radv_amdgpu_cs(cs_array[cs_count - 1]); struct radv_amdgpu_winsys *ws = last_cs->ws; - /* Get the BO list. Assume continue preambles and postambles don't need more. */ struct drm_amdgpu_bo_list_entry *handles = NULL; unsigned num_handles = 0; + + unsigned num_extra_cs = initial_preamble_count + continue_preamble_count + postamble_count; + unsigned extra_cs_idx = 0; + + STACK_ARRAY(struct radeon_cmdbuf *, extra_cs, num_extra_cs); + + for (unsigned i = 0; i < initial_preamble_count; i++) + extra_cs[extra_cs_idx++] = initial_preamble_cs[i]; + for (unsigned i = 0; i < continue_preamble_count; i++) + extra_cs[extra_cs_idx++] = continue_preamble_cs[i]; + for (unsigned i = 0; i < postamble_count; i++) + extra_cs[extra_cs_idx++] = postamble_cs[i]; + u_rwlock_rdlock(&ws->global_bo_list.lock); - result = radv_amdgpu_get_bo_list(ws, &cs_array[0], cs_count, NULL, 0, initial_preamble_cs, - initial_preamble_count, &num_handles, &handles); + result = radv_amdgpu_get_bo_list(ws, &cs_array[0], cs_count, NULL, 0, extra_cs, num_extra_cs, + &num_handles, &handles); if (result != VK_SUCCESS) goto fail; @@ -993,6 +1005,7 @@ radv_amdgpu_winsys_cs_submit_internal( radv_assign_last_submit(ctx, &request); fail: + STACK_ARRAY_FINISH(extra_cs); u_rwlock_rdunlock(&ws->global_bo_list.lock); return result; }