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i965/vec4: Plumb separate surfaces and samplers through from NIR

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This commit is contained in:
Jason Ekstrand 2015-11-02 18:39:17 -08:00
parent 3dd84822df
commit c7d504ad93
3 changed files with 30 additions and 13 deletions
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4
src/mesa/drivers/dri/i965/brw_vec4.h
View file

@ -273,9 +273,11 @@ public:
src_reg offset_value,
src_reg mcs,
bool is_cube_array,
uint32_t surface, src_reg surface_reg,
uint32_t sampler, src_reg sampler_reg);
uint32_t gather_channel(unsigned gather_component, uint32_t sampler);
uint32_t gather_channel(unsigned gather_component,
uint32_t surface, uint32_t sampler);
src_reg emit_mcs_fetch(const glsl_type *coordinate_type, src_reg coordinate,
src_reg sampler);
void emit_gen6_gather_wa(uint8_t wa, dst_reg dst);

27
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
View file

@ -1574,7 +1574,9 @@ glsl_type_for_nir_alu_type(nir_alu_type alu_type,
void
vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
{
unsigned texture = instr->texture_index;
unsigned sampler = instr->sampler_index;
src_reg texture_reg = src_reg(texture);
src_reg sampler_reg = src_reg(sampler);
src_reg coordinate;
const glsl_type *coord_type = NULL;
@ -1655,8 +1657,8 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
sample_index = get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_D, 1);
assert(coord_type != NULL);
if (devinfo->gen >= 7 &&
key_tex->compressed_multisample_layout_mask & (1 << sampler)) {
mcs = emit_mcs_fetch(coord_type, coordinate, sampler_reg);
key_tex->compressed_multisample_layout_mask & (1 << texture)) {
mcs = emit_mcs_fetch(coord_type, coordinate, texture_reg);
} else {
mcs = src_reg(0u);
}
@ -1668,13 +1670,12 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
offset_value = get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_D, 2);
break;
case nir_tex_src_sampler_offset: {
/* The highest sampler which may be used by this operation is
case nir_tex_src_texture_offset: {
/* The highest texture which may be used by this operation is
* the last element of the array. Mark it here, because the generator
* doesn't have enough information to determine the bound.
*/
uint32_t array_size = instr->texture_array_size;
uint32_t max_used = sampler + array_size - 1;
uint32_t max_used = texture + instr->texture_array_size - 1;
if (instr->op == nir_texop_tg4) {
max_used += prog_data->base.binding_table.gather_texture_start;
} else {
@ -1683,6 +1684,15 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
brw_mark_surface_used(&prog_data->base, max_used);
/* Emit code to evaluate the actual indexing expression */
src_reg src = get_nir_src(instr->src[i].src, 1);
src_reg temp(this, glsl_type::uint_type);
emit(ADD(dst_reg(temp), src, src_reg(texture)));
texture_reg = emit_uniformize(temp);
break;
}
case nir_tex_src_sampler_offset: {
/* Emit code to evaluate the actual indexing expression */
src_reg src = get_nir_src(instr->src[i].src, 1);
src_reg temp(this, glsl_type::uint_type);
@ -1712,7 +1722,7 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
/* Stuff the channel select bits in the top of the texture offset */
if (instr->op == nir_texop_tg4)
constant_offset |= gather_channel(instr->component, sampler) << 16;
constant_offset |= gather_channel(instr->component, texture, sampler) << 16;
ir_texture_opcode op = ir_texture_opcode_for_nir_texop(instr->op);
@ -1725,7 +1735,8 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
shadow_comparitor,
lod, lod2, sample_index,
constant_offset, offset_value,
mcs, is_cube_array, sampler, sampler_reg);
mcs, is_cube_array,
texture, texture_reg, sampler, sampler_reg);
}
void

12
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
View file

@ -877,6 +877,8 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
src_reg offset_value,
src_reg mcs,
bool is_cube_array,
uint32_t surface,
src_reg surface_reg,
uint32_t sampler,
src_reg sampler_reg)
{
@ -936,7 +938,8 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
inst->dst.writemask = WRITEMASK_XYZW;
inst->shadow_compare = shadow_comparitor.file != BAD_FILE;
inst->src[1] = sampler_reg;
inst->src[1] = surface_reg;
inst->src[2] = sampler_reg;
/* MRF for the first parameter */
int param_base = inst->base_mrf + inst->header_size;
@ -1062,7 +1065,7 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
}
if (devinfo->gen == 6 && op == ir_tg4) {
emit_gen6_gather_wa(key_tex->gen6_gather_wa[sampler], inst->dst);
emit_gen6_gather_wa(key_tex->gen6_gather_wa[surface], inst->dst);
}
swizzle_result(op, dest,
@ -1100,7 +1103,8 @@ vec4_visitor::emit_gen6_gather_wa(uint8_t wa, dst_reg dst)
* Set up the gather channel based on the swizzle, for gather4.
*/
uint32_t
vec4_visitor::gather_channel(unsigned gather_component, uint32_t sampler)
vec4_visitor::gather_channel(unsigned gather_component,
uint32_t surface, uint32_t sampler)
{
int swiz = GET_SWZ(key_tex->swizzles[sampler], gather_component);
switch (swiz) {
@ -1109,7 +1113,7 @@ vec4_visitor::gather_channel(unsigned gather_component, uint32_t sampler)
/* gather4 sampler is broken for green channel on RG32F --
* we must ask for blue instead.
*/
if (key_tex->gather_channel_quirk_mask & (1 << sampler))
if (key_tex->gather_channel_quirk_mask & (1 << surface))
return 2;
return 1;
case SWIZZLE_Z: return 2;