From c7bcbc950c04367c6abf54cb48ef930557dcea60 Mon Sep 17 00:00:00 2001 From: Nanley Chery Date: Fri, 30 Jul 2021 14:31:05 -0700 Subject: [PATCH] intel/blorp: Fix Gfx7 stencil surface state valign Stencil on Gfx7 has a vertical alignment element of 8, but the largest its surface state can express is 4. Apply the Gfx6 solution of changing the alignment in blorp_surf_retile_w_to_y. Cc: mesa-stable Reviewed-by: Jason Ekstrand Part-of: --- src/intel/blorp/blorp_blit.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c index cd29f65cd2e..f69fa18e633 100644 --- a/src/intel/blorp/blorp_blit.c +++ b/src/intel/blorp/blorp_blit.c @@ -1650,8 +1650,8 @@ blorp_surf_retile_w_to_y(const struct isl_device *isl_dev, blorp_surf_fake_interleaved_msaa(isl_dev, info); } - if (isl_dev->info->ver == 6) { - /* Gfx6 stencil buffers have a very large alignment coming in from the + if (isl_dev->info->ver == 6 || isl_dev->info->ver == 7) { + /* Gfx6-7 stencil buffers have a very large alignment coming in from the * miptree. It's out-of-bounds for what the surface state can handle. * Since we have a single layer and level, it doesn't really matter as * long as we don't pass a bogus value into isl_surf_fill_state().