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radv: vectorize float8 conversions

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Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35434>
This commit is contained in:
Georg Lehmann 2025-04-09 14:31:26 +02:00 • committed by Marge Bot
parent 001cd632ee
commit c7a6b3318e
1 changed files with 15 additions and 2 deletions
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17
src/amd/vulkan/radv_pipeline.c
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@ -265,6 +265,20 @@ opt_vectorize_callback(const nir_instr *instr, const void *_)
return 1;
const nir_alu_instr *alu = nir_instr_as_alu(instr);
switch (alu->op) {
case nir_op_f2e4m3fn:
case nir_op_f2e4m3fn_sat:
case nir_op_f2e4m3fn_satfn:
case nir_op_f2e5m2:
case nir_op_f2e5m2_sat:
case nir_op_e4m3fn2f:
case nir_op_e5m22f:
return 2;
default:
break;
}
const unsigned bit_size = alu->def.bit_size;
if (bit_size != 16)
return 1;
@ -587,8 +601,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat
NIR_PASS(_, stage->nir, nir_opt_dce);
}
if (!stage->key.optimisations_disabled &&
((stage->nir->info.bit_sizes_int | stage->nir->info.bit_sizes_float) & 16)) {
if (!stage->key.optimisations_disabled) {
NIR_PASS(_, stage->nir, nir_opt_vectorize, opt_vectorize_callback, device);
}
}