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nak: Add a bunch of shader lowering code in NIR
The nifty thing about the way NVIDIA hardware does inputs and outputs is that it maps really well to how we do them in NIR. We can make the driver_locations match exactly to the attribute address space. For fragment shader outputs, we make them register numbers. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24998>
This commit is contained in:
Faith Ekstrand
Marge Bot
parent
1b70f39ef6
commit
c778d39fa4
1 changed files with 248 additions and 0 deletions
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@ -109,9 +109,257 @@ nak_optimize_nir(nir_shader *nir, const struct nak_compiler *nak)
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void
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nak_preprocess_nir(nir_shader *nir, const struct nak_compiler *nak)
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{
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UNUSED bool progress = false;
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nir_validate_ssa_dominance(nir, "before nak_preprocess_nir");
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const nir_lower_tex_options tex_options = {
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.lower_txp = ~0,
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/* TODO: More lowering */
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};
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OPT(nir, nir_lower_tex, &tex_options);
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OPT(nir, nir_lower_global_vars_to_local);
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OPT(nir, nir_split_var_copies);
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OPT(nir, nir_split_struct_vars, nir_var_function_temp);
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/* Optimize but allow copies because we haven't lowered them yet */
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optimize_nir(nir, nak, true /* allow_copies */);
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OPT(nir, nir_lower_load_const_to_scalar);
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OPT(nir, nir_lower_var_copies);
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OPT(nir, nir_lower_system_values);
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OPT(nir, nir_lower_compute_system_values, NULL);
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}
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static uint16_t
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nak_attribute_attr_addr(gl_vert_attrib attrib)
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{
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assert(attrib >= VERT_ATTRIB_GENERIC0);
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return 0x80 + (attrib - VERT_ATTRIB_GENERIC0) * 0x10;
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}
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static int
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count_location_bytes(const struct glsl_type *type, bool bindless)
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{
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return glsl_count_attribute_slots(type, false) * 16;
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}
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static bool
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nak_nir_lower_vs_inputs(nir_shader *nir)
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{
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bool progress = false;
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nir_foreach_shader_in_variable(var, nir) {
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var->data.driver_location =
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nak_attribute_attr_addr(var->data.location);
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}
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progress |= OPT(nir, nir_lower_io, nir_var_shader_in, count_location_bytes,
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nir_lower_io_lower_64bit_to_32);
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return progress;
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}
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static uint16_t
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nak_varying_attr_addr(gl_varying_slot slot)
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{
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if (slot >= VARYING_SLOT_PATCH0) {
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return 0x020 + (slot - VARYING_SLOT_PATCH0) * 0x10;
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} else if (slot >= VARYING_SLOT_VAR0) {
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return 0x080 + (slot - VARYING_SLOT_VAR0) * 0x10;
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} else {
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switch (slot) {
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case VARYING_SLOT_TESS_LEVEL_OUTER: return 0x000;
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case VARYING_SLOT_TESS_LEVEL_INNER: return 0x010;
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case VARYING_SLOT_PRIMITIVE_ID: return 0x060;
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case VARYING_SLOT_LAYER: return 0x064;
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case VARYING_SLOT_VIEWPORT: return 0x068;
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case VARYING_SLOT_PSIZ: return 0x06c;
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case VARYING_SLOT_POS: return 0x070;
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case VARYING_SLOT_CLIP_DIST0: return 0x2c0;
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case VARYING_SLOT_CLIP_DIST1: return 0x2d0;
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default: unreachable("Invalid varying slot");
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}
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}
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}
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static bool
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nak_nir_lower_varyings(nir_shader *nir, nir_variable_mode modes)
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{
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bool progress = false;
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assert(!(modes & ~(nir_var_shader_in | nir_var_shader_out)));
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nir_foreach_variable_with_modes(var, nir, modes)
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var->data.driver_location = nak_varying_attr_addr(var->data.location);
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progress |= OPT(nir, nir_lower_io, modes, count_location_bytes, 0);
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return progress;
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}
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static int
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vec_size_4(const struct glsl_type *type, bool bindless)
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{
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assert(glsl_type_is_vector_or_scalar(type));
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return 4;
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}
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static bool
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nak_nir_lower_fs_outputs(nir_shader *nir)
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{
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const uint32_t color_targets =
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(nir->info.outputs_written & BITFIELD_BIT(FRAG_RESULT_COLOR)) ?
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1 : (nir->info.outputs_written >> FRAG_RESULT_DATA0);
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const bool writes_depth =
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nir->info.outputs_written & BITFIELD_BIT(FRAG_RESULT_DEPTH);
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const bool writes_sample_mask =
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nir->info.outputs_written & BITFIELD_BIT(FRAG_RESULT_SAMPLE_MASK);
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nir->num_outputs = util_bitcount(color_targets) * 4 +
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writes_depth + writes_sample_mask;
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nir_foreach_shader_out_variable(var, nir) {
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assert(nir->info.outputs_written & BITFIELD_BIT(var->data.location));
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switch (var->data.location) {
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case FRAG_RESULT_DEPTH:
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var->data.driver_location = util_bitcount(color_targets) * 4;
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break;
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case FRAG_RESULT_COLOR:
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var->data.driver_location = 0;
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break;
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case FRAG_RESULT_SAMPLE_MASK:
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var->data.driver_location = util_bitcount(color_targets) * 4;
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var->data.driver_location += writes_depth;
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break;
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default: {
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assert(var->data.location >= FRAG_RESULT_DATA0);
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const unsigned out = var->data.location - FRAG_RESULT_DATA0;
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var->data.driver_location =
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util_bitcount(color_targets & BITFIELD_MASK(out));
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break;
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}
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}
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}
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bool progress = nir->info.outputs_written != 0;
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progress |= OPT(nir, nir_lower_io, nir_var_shader_out, vec_size_4, 0);
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return progress;
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}
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static uint16_t
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nak_sysval_attr_addr(gl_system_value sysval)
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{
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switch (sysval) {
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case SYSTEM_VALUE_FRAG_COORD: return 0x070;
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case SYSTEM_VALUE_POINT_COORD: return 0x2e0;
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case SYSTEM_VALUE_TESS_COORD: return 0x2f0;
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case SYSTEM_VALUE_INSTANCE_ID: return 0x2f8;
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case SYSTEM_VALUE_VERTEX_ID: return 0x2fc;
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default: unreachable("Invalid system value");
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}
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}
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static bool
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nak_nir_lower_system_value_instr(nir_builder *b, nir_instr *instr, void *data)
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{
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if (instr->type != nir_instr_type_intrinsic)
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return false;
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b->cursor = nir_before_instr(instr);
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nir_def *val;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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switch (intrin->intrinsic) {
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case nir_intrinsic_load_sample_pos: {
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const uint32_t addr = nak_sysval_attr_addr(SYSTEM_VALUE_FRAG_COORD);
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val = nir_load_input(b, 2, 32, nir_imm_int(b, 0), .base = addr,
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.dest_type = nir_type_float32);
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val = nir_ffract(b, val);
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break;
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}
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case nir_intrinsic_load_layer_id: {
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const uint32_t addr = nak_varying_attr_addr(VARYING_SLOT_LAYER);
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val = nir_load_input(b, intrin->def.num_components, 32,
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nir_imm_int(b, 0), .base = addr,
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.dest_type = nir_type_int32);
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break;
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}
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case nir_intrinsic_load_frag_coord:
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case nir_intrinsic_load_point_coord:
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case nir_intrinsic_load_tess_coord:
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case nir_intrinsic_load_instance_id:
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case nir_intrinsic_load_vertex_id: {
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const gl_system_value sysval =
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nir_system_value_from_intrinsic(intrin->intrinsic);
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const uint32_t addr = nak_sysval_attr_addr(sysval);
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val = nir_load_input(b, intrin->def.num_components, 32,
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nir_imm_int(b, 0), .base = addr,
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.dest_type = nir_type_int32);
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break;
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}
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default:
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return false;
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}
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nir_def_rewrite_uses(&intrin->def, val);
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return true;
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}
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static bool
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nak_nir_lower_system_values(nir_shader *nir)
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{
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return nir_shader_instructions_pass(nir, nak_nir_lower_system_value_instr,
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nir_metadata_block_index |
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nir_metadata_dominance,
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NULL);
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}
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void
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nak_postprocess_nir(nir_shader *nir, const struct nak_compiler *nak)
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{
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UNUSED bool progress = false;
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OPT(nir, nir_lower_int64);
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nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
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switch (nir->info.stage) {
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case MESA_SHADER_VERTEX:
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OPT(nir, nak_nir_lower_vs_inputs);
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OPT(nir, nak_nir_lower_varyings, nir_var_shader_out);
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break;
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case MESA_SHADER_FRAGMENT:
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OPT(nir, nak_nir_lower_varyings, nir_var_shader_in);
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OPT(nir, nak_nir_lower_fs_outputs);
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break;
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case MESA_SHADER_COMPUTE:
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case MESA_SHADER_KERNEL:
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break;
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default:
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unreachable("Unsupported shader stage");
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}
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OPT(nir, nak_nir_lower_system_values);
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nak_optimize_nir(nir, nak);
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nir_divergence_analysis(nir);
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/* Compact SSA defs because we'll use them to index arrays */
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nir_foreach_function(func, nir) {
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if (func->impl)
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nir_index_ssa_defs(func->impl);
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}
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nir_print_shader(nir, stderr);
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}
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