diff --git a/src/freedreno/common/freedreno_dev_info.h b/src/freedreno/common/freedreno_dev_info.h index 9debe894ea9..4599a8af5e0 100644 --- a/src/freedreno/common/freedreno_dev_info.h +++ b/src/freedreno/common/freedreno_dev_info.h @@ -122,21 +122,6 @@ struct fd_dev_info { bool has_8bpp_ubwc; - /* a650 seems to be affected by a bug where flushing CCU color into - * depth or vice-versa requires a WFI. In particular, clearing a - * depth attachment (which writes to it as a color attachment) then - * using it as a normal depth attachment requires a WFI in addition - * to the expected CCU_FLUSH_COLOR + CCU_INVALIDATE_DEPTH, even - * though all those operations happen in the same stage. As this is - * usually the only scenario where a CCU flush doesn't require a WFI - * we just insert a WFI after every CCU flush. - * - * Tests affected include - * dEQP-VK.renderpass.suballocation.formats.d16_unorm.* in sysmem - * mode (a few tests flake when the entire series is run). - */ - bool has_ccu_flush_bug; - bool has_lpac; bool has_getfiberid; diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py index c059125e74b..dd14d24032a 100644 --- a/src/freedreno/common/freedreno_devices.py +++ b/src/freedreno/common/freedreno_devices.py @@ -293,7 +293,6 @@ a6xx_gen3 = dict( has_tex_filter_cubic = True, has_separate_chroma_filter = True, has_sample_locations = True, - has_ccu_flush_bug = True, has_8bpp_ubwc = False, has_dp2acc = True, has_lrz_dir_tracking = True, @@ -316,7 +315,6 @@ a6xx_gen4 = dict( has_tex_filter_cubic = True, has_separate_chroma_filter = True, has_sample_locations = True, - has_ccu_flush_bug = True, has_cp_reg_write = False, has_8bpp_ubwc = False, has_lpac = True, diff --git a/src/freedreno/vulkan/tu_clear_blit.cc b/src/freedreno/vulkan/tu_clear_blit.cc index eb87d50c9b6..d50c7144b20 100644 --- a/src/freedreno/vulkan/tu_clear_blit.cc +++ b/src/freedreno/vulkan/tu_clear_blit.cc @@ -3193,8 +3193,7 @@ tu_clear_sysmem_attachment(struct tu_cmd_buffer *cmd, tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_COLOR); } - if (cmd->device->physical_device->info->a6xx.has_ccu_flush_bug) - tu_cs_emit_wfi(cs); + tu_cs_emit_wfi(cs); } void diff --git a/src/freedreno/vulkan/tu_cmd_buffer.cc b/src/freedreno/vulkan/tu_cmd_buffer.cc index c63ae7dfe36..5214951db2f 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.cc +++ b/src/freedreno/vulkan/tu_cmd_buffer.cc @@ -175,9 +175,7 @@ tu6_emit_flushes(struct tu_cmd_buffer *cmd_buffer, } if (flushes & TU_CMD_FLAG_WAIT_MEM_WRITES) tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0); - if ((flushes & TU_CMD_FLAG_WAIT_FOR_IDLE) || - (cmd_buffer->device->physical_device->info->a6xx.has_ccu_flush_bug && - (flushes & (TU_CMD_FLAG_CCU_FLUSH_COLOR | TU_CMD_FLAG_CCU_FLUSH_DEPTH)))) + if (flushes & TU_CMD_FLAG_WAIT_FOR_IDLE) tu_cs_emit_wfi(cs); if (flushes & TU_CMD_FLAG_WAIT_FOR_ME) tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_barrier.cc b/src/gallium/drivers/freedreno/a6xx/fd6_barrier.cc index 9a3d92949fb..ca2513d8fd4 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_barrier.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_barrier.cc @@ -94,9 +94,7 @@ fd6_emit_flushes(struct fd_context *ctx, struct fd_ringbuffer *ring, if (flushes & FD6_WAIT_MEM_WRITES) OUT_PKT7(ring, CP_WAIT_MEM_WRITES, 0); - if ((flushes & FD6_WAIT_FOR_IDLE) || - (ctx->screen->info->a6xx.has_ccu_flush_bug && - (flushes & (FD6_FLUSH_CCU_COLOR | FD6_FLUSH_CCU_DEPTH)))) + if (flushes & FD6_WAIT_FOR_IDLE) OUT_PKT7(ring, CP_WAIT_FOR_IDLE, 0); if (flushes & FD6_WAIT_FOR_ME) diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_blitter.cc b/src/gallium/drivers/freedreno/a6xx/fd6_blitter.cc index 72e0b92fc15..7fc0b1012ed 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_blitter.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_blitter.cc @@ -546,7 +546,8 @@ fd6_clear_ubwc(struct fd_batch *batch, struct fd_resource *rsc) assert_dt fd6_emit_flushes(batch->ctx, ring, FD6_FLUSH_CCU_COLOR | FD6_FLUSH_CCU_DEPTH | - FD6_FLUSH_CACHE); + FD6_FLUSH_CACHE | + FD6_WAIT_FOR_IDLE); } static void @@ -1006,7 +1007,8 @@ fd6_clear_texture(struct pipe_context *pctx, struct pipe_resource *prsc, fd6_emit_flushes(batch->ctx, batch->draw, FD6_FLUSH_CCU_COLOR | FD6_FLUSH_CCU_DEPTH | - FD6_FLUSH_CACHE); + FD6_FLUSH_CACHE | + FD6_WAIT_FOR_IDLE); fd_batch_flush(batch); fd_batch_reference(&batch, NULL); @@ -1095,7 +1097,8 @@ fd6_resolve_tile(struct fd_batch *batch, struct fd_ringbuffer *ring, * sysmem, and we generally assume that GMEM renderpasses leave their * results in sysmem, so we need to flush manually here. */ - fd6_emit_flushes(batch->ctx, ring, FD6_FLUSH_CCU_COLOR); + fd6_emit_flushes(batch->ctx, ring, + FD6_FLUSH_CCU_COLOR | FD6_WAIT_FOR_IDLE); } template void fd6_resolve_tile(struct fd_batch *batch, struct fd_ringbuffer *ring, @@ -1164,7 +1167,8 @@ handle_rgba_blit(struct fd_context *ctx, fd6_emit_flushes(batch->ctx, batch->draw, FD6_FLUSH_CCU_COLOR | FD6_FLUSH_CCU_DEPTH | - FD6_FLUSH_CACHE); + FD6_FLUSH_CACHE | + FD6_WAIT_FOR_IDLE); fd_batch_flush(batch); fd_batch_reference(&batch, NULL);