diff --git a/src/intel/compiler/brw_compile_bs.cpp b/src/intel/compiler/brw_compile_bs.cpp
index 4b82398a2e6..4d11d05cd04 100644
--- a/src/intel/compiler/brw_compile_bs.cpp
+++ b/src/intel/compiler/brw_compile_bs.cpp
@@ -78,19 +78,19 @@ compile_single_bs(const struct brw_compiler *compiler,
    prog_data->max_stack_size = MAX2(prog_data->max_stack_size,
                                     shader->scratch_size);
 
-   const unsigned max_dispatch_width = 16;
-   brw_nir_apply_key(shader, compiler, &key->base, max_dispatch_width);
+   /* Since divergence is a lot more likely in RT than compute, it makes
+    * sense to limit ourselves to the smallest available SIMD for now.
+    */
+   const unsigned required_width = compiler->devinfo->ver >= 20 ? 16u : 8u;
+
+   brw_nir_apply_key(shader, compiler, &key->base, required_width);
    brw_postprocess_nir(shader, compiler, debug_enabled,
                        key->base.robust_flags);
 
    brw_simd_selection_state simd_state{
       .devinfo = compiler->devinfo,
       .prog_data = prog_data,
-
-      /* Since divergence is a lot more likely in RT than compute, it makes
-       * sense to limit ourselves to the smallest available SIMD for now.
-       */
-      .required_width = compiler->devinfo->ver >= 20 ? 16u : 8u,
+      .required_width = required_width,
    };
 
    std::unique_ptr<brw_shader> v[2];