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anv: Improve BTI change cache flushing

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This commit makes two changes:

 1. We set pending_pipe_bits instead of emitting PIPE_CONTROL directly
    for the flush at the end of cmd_buffer_begin_subpass.

 2. Because BLORP ops such as vkCmdClearAttachments may come in the
    middle of a render pass, we have to also flag the need for a cache
    flush after the blorp op.

Fixes: 185630c6bc "anv/blorp: Do the gen11 BTI flush"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3547>
This commit is contained in:
Jason Ekstrand 2020-01-22 22:37:10 -06:00 • committed by Marge Bot
parent e39c52787e
commit c70a786c77
2 changed files with 17 additions and 7 deletions
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14
src/intel/vulkan/genX_blorp_exec.c
View file

@ -272,6 +272,20 @@ genX(blorp_exec)(struct blorp_batch *batch,
blorp_exec(batch, params);
#if GEN_GEN >= 11
/* The PIPE_CONTROL command description says:
*
* "Whenever a Binding Table Index (BTI) used by a Render Taget Message
* points to a different RENDER_SURFACE_STATE, SW must issue a Render
* Target Cache Flush by enabling this bit. When render target flush
* is set due to new association of BTI, PS Scoreboard Stall bit must
* be set in this packet."
*/
cmd_buffer->state.pending_pipe_bits |=
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
#endif
cmd_buffer->state.gfx.vb_dirty = ~0;
cmd_buffer->state.gfx.dirty = ~0;
cmd_buffer->state.push_constants_dirty = ~0;

10
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -4910,13 +4910,9 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer,
* is set due to new association of BTI, PS Scoreboard Stall bit must
* be set in this packet."
*/
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.RenderTargetCacheFlushEnable = true;
pc.StallAtPixelScoreboard = true;
#if GEN_GEN >= 12
pc.TileCacheFlushEnable = true;
#endif
}
cmd_buffer->state.pending_pipe_bits |=
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
#endif
}