diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 806a7639f77..b16c68d4da4 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -6179,6 +6179,7 @@ radv_emit_tess_domain_origin_state(struct radv_cmd_buffer *cmd_buffer)
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
    const struct radv_physical_device *pdev = radv_device_physical(device);
    const struct radv_shader *tes = radv_get_shader(cmd_buffer->state.shaders, MESA_SHADER_TESS_EVAL);
+   const struct radv_shader *tcs = cmd_buffer->state.shaders[MESA_SHADER_TESS_CTRL];
    const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
    unsigned type = 0, partitioning = 0;
    unsigned topology;
@@ -6200,7 +6201,10 @@ radv_emit_tess_domain_origin_state(struct radv_cmd_buffer *cmd_buffer)
       UNREACHABLE("Invalid tess primitive type");
    }
 
-   switch (tes->info.tes.spacing) {
+   const uint32_t tess_spacing =
+      tes->info.tes.spacing == TESS_SPACING_UNSPECIFIED ? tcs->info.tcs.spacing : tes->info.tes.spacing;
+
+   switch (tess_spacing) {
    case TESS_SPACING_EQUAL:
       partitioning = V_028B6C_PART_INTEGER;
       break;
@@ -6214,12 +6218,14 @@ radv_emit_tess_domain_origin_state(struct radv_cmd_buffer *cmd_buffer)
       UNREACHABLE("Invalid tess spacing type");
    }
 
-   if (tes->info.tes.point_mode) {
+   const bool point_mode = tes->info.tes.point_mode | tcs->info.tcs.point_mode;
+
+   if (point_mode) {
       topology = V_028B6C_OUTPUT_POINT;
    } else if (tes->info.tes._primitive_mode == TESS_PRIMITIVE_ISOLINES) {
       topology = V_028B6C_OUTPUT_LINE;
    } else {
-      bool ccw = tes->info.tes.ccw;
+      bool ccw = tes->info.tes.ccw | tcs->info.tcs.ccw;
 
       if (d->vk.ts.domain_origin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT) {
          ccw = !ccw;
diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c
index 35860206264..34b46dcc759 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -589,6 +589,9 @@ gather_shader_info_tcs(struct radv_device *device, const nir_shader *nir,
    nir_gather_tcs_info(nir, &tcs_info, nir->info.tess._primitive_mode, nir->info.tess.spacing);
    ac_nir_get_tess_io_info(nir, &tcs_info, ~0ull, ~0, map_output, true, &info->tcs.io_info);
 
+   info->tcs.spacing = nir->info.tess.spacing;
+   info->tcs.ccw = nir->info.tess.ccw;
+   info->tcs.point_mode = nir->info.tess.point_mode;
    info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
    info->tcs.tes_inputs_read = ~0ULL;
    info->tcs.tes_patch_inputs_read = ~0ULL;
diff --git a/src/amd/vulkan/radv_shader_info.h b/src/amd/vulkan/radv_shader_info.h
index d3af488d966..55504e31178 100644
--- a/src/amd/vulkan/radv_shader_info.h
+++ b/src/amd/vulkan/radv_shader_info.h
@@ -241,6 +241,9 @@ struct radv_shader_info {
       uint32_t tcs_vertices_out;
       uint32_t lds_size;         /* in bytes */
       uint8_t num_linked_inputs; /* Number of reserved per-vertex input slots in LDS. */
+      enum gl_tess_spacing spacing;
+      bool ccw;
+      bool point_mode;
       bool tes_reads_tess_factors : 1;
    } tcs;
    struct {