diff --git a/src/gallium/drivers/iris/iris_resource.c b/src/gallium/drivers/iris/iris_resource.c index 714d82b2017..0671ba95450 100644 --- a/src/gallium/drivers/iris/iris_resource.c +++ b/src/gallium/drivers/iris/iris_resource.c @@ -2587,7 +2587,7 @@ iris_transfer_map(struct pipe_context *ctx, usage |= PIPE_MAP_DIRECTLY; /* TODO: Teach iris_map_tiled_memcpy about Tile64... */ - if (res->surf.tiling == ISL_TILING_64) + if (isl_tiling_is_64(res->surf.tiling)) usage &= ~PIPE_MAP_DIRECTLY; if (!(usage & PIPE_MAP_DIRECTLY)) { @@ -2715,7 +2715,7 @@ iris_texture_subdata(struct pipe_context *ctx, * TODO: Teach isl_memcpy_linear_to_tiled about Tile64... */ if (surf->tiling == ISL_TILING_LINEAR || - surf->tiling == ISL_TILING_64 || + isl_tiling_is_64(res->surf.tiling) || isl_aux_usage_has_compression(res->aux.usage) || resource_is_busy(ice, res) || iris_bo_mmap_mode(res->bo) == IRIS_MMAP_NONE) { diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c index 21eadd93803..c5077da1d59 100644 --- a/src/intel/blorp/blorp_blit.c +++ b/src/intel/blorp/blorp_blit.c @@ -2838,7 +2838,7 @@ blorp_surf_convert_to_uncompressed(const struct isl_device *isl_dev, * tilings don't need intratile offsets because each subresource is aligned * to a bpb-based tile boundary or miptail slot offset. */ - if (info->surf.tiling == ISL_TILING_64 || + if (isl_tiling_is_64(info->surf.tiling) || isl_tiling_is_std_y(info->surf.tiling)) { assert(info->tile_x_sa == 0 && info->tile_y_sa == 0); } else { diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h index 09c184abcd0..7e41bed94f9 100644 --- a/src/intel/blorp/blorp_genX_exec.h +++ b/src/intel/blorp/blorp_genX_exec.h @@ -2335,6 +2335,7 @@ xy_bcb_tiling(const struct isl_surf *surf) case ISL_TILING_4: return XY_TILE_4; case ISL_TILING_64: + case ISL_TILING_64_XE2: return XY_TILE_64; #else case ISL_TILING_Y0: diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 0d1e94a1314..4af748af6b5 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -562,6 +562,8 @@ tiling_max_mip_tail(enum isl_tiling tiling, { /* In theory, miptails work for multisampled images, but we don't support * mipmapped multisampling. + * + * BSpec 58770: Xe2 does not support miptails on multisampled images. */ if (samples > 1) return 0; @@ -610,6 +612,7 @@ tiling_max_mip_tail(enum isl_tiling tiling, break; case ISL_TILING_64: + case ISL_TILING_64_XE2: /* ATS-M PRMS, Volume 5: Memory Data Formats : * * - Tiling and Mip Tail for 1D Surfaces : @@ -840,6 +843,85 @@ isl_tiling_get_info(enum isl_tiling tiling, } } +#undef tile_extent2d +#undef tile_extent3d + + phys_B.w = logical_el.w * bs; + phys_B.h = 64 * 1024 / phys_B.w; + break; + + case ISL_TILING_64_XE2: + /* The tables below are taken from BSpec 58767 which are formulated in + * terms of the Cv and Cu constants. This is different from the tables in + * the "Tile64 Format" page which should be equivalent but are usually in + * terms of pixels. + * + * Also note that Cv and Cu are HxW order to match the Bspec table, not + * WxH order like you might expect. + */ +#define tile_extent2d(bs, cv, cu, a) \ + isl_extent4d((1 << cu) / bs, 1 << cv, 1, a) +#define tile_extent3d(bs, cr, cv, cu) \ + isl_extent4d((1 << cu) / bs, 1 << cv, 1 << cr, 1) + + if (dim == ISL_SURF_DIM_3D) { + switch (format_bpb) { + case 128: logical_el = tile_extent3d(bs, 4, 4, 8); break; + case 64: logical_el = tile_extent3d(bs, 4, 4, 8); break; + case 32: logical_el = tile_extent3d(bs, 4, 5, 7); break; + case 16: logical_el = tile_extent3d(bs, 5, 5, 6); break; + case 8: logical_el = tile_extent3d(bs, 5, 5, 6); break; + default: unreachable("Unsupported format size for 3D"); + } + } else { + if (samples == 1 || msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED) { + switch (format_bpb) { + case 128: logical_el = tile_extent2d(bs, 6, 10, 1); break; + case 64: logical_el = tile_extent2d(bs, 6, 10, 1); break; + case 32: logical_el = tile_extent2d(bs, 7, 9, 1); break; + case 16: logical_el = tile_extent2d(bs, 7, 9, 1); break; + case 8: logical_el = tile_extent2d(bs, 8, 8, 1); break; + default: unreachable("Unsupported format size."); + } + } else if (samples == 2) { + switch (format_bpb) { + case 128: logical_el = tile_extent2d(bs, 5, 10, 2); break; + case 64: logical_el = tile_extent2d(bs, 6, 9, 2); break; + case 32: logical_el = tile_extent2d(bs, 7, 8, 2); break; + case 16: logical_el = tile_extent2d(bs, 7, 8, 2); break; + case 8: logical_el = tile_extent2d(bs, 8, 7, 2); break; + default: unreachable("Unsupported format size."); + } + } else if (samples == 4) { + switch (format_bpb) { + case 128: logical_el = tile_extent2d(bs, 5, 9, 4); break; + case 64: logical_el = tile_extent2d(bs, 5, 9, 4); break; + case 32: logical_el = tile_extent2d(bs, 6, 8, 4); break; + case 16: logical_el = tile_extent2d(bs, 6, 8, 4); break; + case 8: logical_el = tile_extent2d(bs, 7, 7, 4); break; + default: unreachable("Unsupported format size."); + } + } else if (samples == 8) { + switch (format_bpb) { + case 128: logical_el = tile_extent2d(bs, 5, 8, 8); break; + case 64: logical_el = tile_extent2d(bs, 5, 8, 8); break; + case 32: logical_el = tile_extent2d(bs, 5, 8, 8); break; + case 16: logical_el = tile_extent2d(bs, 6, 7, 8); break; + case 8: logical_el = tile_extent2d(bs, 6, 7, 8); break; + default: unreachable("Unsupported format size."); + } + } else if (samples == 16) { + switch (format_bpb) { + case 128: logical_el = tile_extent2d(bs, 4, 8, 16); break; + case 64: logical_el = tile_extent2d(bs, 5, 7, 16); break; + case 32: logical_el = tile_extent2d(bs, 5, 7, 16); break; + case 16: logical_el = tile_extent2d(bs, 5, 7, 16); break; + case 8: logical_el = tile_extent2d(bs, 6, 6, 16); break; + default: unreachable("Unsupported format size."); + } + } + } + #undef tile_extent2d #undef tile_extent3d @@ -1026,7 +1108,7 @@ isl_surf_choose_tiling(const struct isl_device *dev, * shapes. */ if (info->usage & ISL_SURF_USAGE_SPARSE_BIT) { - CHOOSE(ISL_TILING_64); + CHOOSE(ISL_GFX_VER(dev) >= 20 ? ISL_TILING_64_XE2 : ISL_TILING_64); CHOOSE(ISL_TILING_ICL_Ys); CHOOSE(ISL_TILING_SKL_Ys); } @@ -1053,7 +1135,7 @@ isl_surf_choose_tiling(const struct isl_device *dev, CHOOSE(ISL_TILING_ICL_Yf); CHOOSE(ISL_TILING_SKL_Ys); CHOOSE(ISL_TILING_ICL_Ys); - CHOOSE(ISL_TILING_64); + CHOOSE(ISL_GFX_VER(dev) >= 20 ? ISL_TILING_64_XE2 : ISL_TILING_64); CHOOSE(ISL_TILING_X); CHOOSE(ISL_TILING_W); @@ -1532,6 +1614,7 @@ isl_get_miptail_level_offset_el(enum isl_tiling tiling, case ISL_SURF_DIM_2D: switch (tiling) { case ISL_TILING_64: + case ISL_TILING_64_XE2: case ISL_TILING_ICL_Yf: case ISL_TILING_ICL_Ys: assert(row < ARRAY_SIZE(icl_std_y_2d_miptail_offset_el)); @@ -1555,6 +1638,7 @@ isl_get_miptail_level_offset_el(enum isl_tiling tiling, case ISL_SURF_DIM_3D: switch (tiling) { case ISL_TILING_64: + case ISL_TILING_64_XE2: assert(row < ARRAY_SIZE(acm_tile64_3d_miptail_offset_el)); assert(col < ARRAY_SIZE(acm_tile64_3d_miptail_offset_el[0])); *x_offset_el = acm_tile64_3d_miptail_offset_el[row][col][0]; @@ -1612,7 +1696,8 @@ isl_choose_miptail_start_level(const struct isl_device *dev, if (ISL_GFX_VER(dev) == 12 && isl_format_is_yuv(info->format)) return 15; - assert(tile_info->tiling == ISL_TILING_64 || isl_tiling_is_std_y(tile_info->tiling)); + assert(isl_tiling_is_64(tile_info->tiling) || + isl_tiling_is_std_y(tile_info->tiling)); assert(info->samples == 1); uint32_t max_miptail_levels = tile_info->max_miptail_levels; @@ -1834,7 +1919,7 @@ isl_calc_phys_slice0_extent_sa_gfx4_2d( if (l >= miptail_start_level) { assert(l == miptail_start_level); - assert(tile_info->tiling == ISL_TILING_64 || + assert(isl_tiling_is_64(tile_info->tiling) || isl_tiling_is_std_y(tile_info->tiling)); assert(w == tile_info->logical_extent_el.w * fmtl->bw); assert(h == tile_info->logical_extent_el.h * fmtl->bh); @@ -1877,7 +1962,7 @@ isl_calc_phys_total_extent_el_gfx4_2d( array_pitch_span, &phys_slice0_sa); - if (tile_info->tiling == ISL_TILING_64 || + if (isl_tiling_is_64(tile_info->tiling) || isl_tiling_is_std_y(tile_info->tiling)) { *phys_total_el = (struct isl_extent4d) { .w = isl_align_div_npot(phys_slice0_sa.w, fmtl->bw), @@ -2903,7 +2988,8 @@ isl_surf_supports_ccs(const struct isl_device *dev, if (surf->miptail_start_level < surf->levels) { const uint32_t miptail_levels = surf->levels - surf->miptail_start_level; if (miptail_levels + isl_get_miptail_base_row(surf->tiling) > 11) { - assert(surf->tiling == ISL_TILING_64 || isl_tiling_is_std_y(surf->tiling)); + assert(isl_tiling_is_64(surf->tiling) || + isl_tiling_is_std_y(surf->tiling)); return false; } } @@ -2993,17 +3079,18 @@ isl_surf_supports_ccs(const struct isl_device *dev, if (ISL_GFX_VER(dev) == 12 && surf->dim == ISL_SURF_DIM_3D && (surf->tiling == ISL_TILING_ICL_Ys || - surf->tiling == ISL_TILING_64) && + isl_tiling_is_64(surf->tiling)) && (format_bpb == 64 || format_bpb == 128)) return false; /* TODO: Handle the other tiling formats */ - if (surf->tiling != ISL_TILING_Y0 && surf->tiling != ISL_TILING_4 && - surf->tiling != ISL_TILING_64) + if (surf->tiling != ISL_TILING_Y0 && + surf->tiling != ISL_TILING_4 && + !isl_tiling_is_64(surf->tiling)) return false; /* TODO: Handle single-sampled Tile64. */ - if (surf->samples == 1 && surf->tiling == ISL_TILING_64) + if (surf->samples == 1 && isl_tiling_is_64(surf->tiling)) return false; } else { /* ISL_GFX_VER(dev) < 12 */ @@ -3207,7 +3294,8 @@ get_image_offset_sa_gfx4_2d(const struct isl_surf *surf, (surf->msaa_layout == ISL_MSAA_LAYOUT_ARRAY ? surf->samples : 1); uint32_t x = 0, y; - if (isl_tiling_is_std_y(surf->tiling) || surf->tiling == ISL_TILING_64) { + if (isl_tiling_is_std_y(surf->tiling) || + isl_tiling_is_64(surf->tiling)) { y = 0; if (surf->dim == ISL_SURF_DIM_3D) { *z_offset_sa = logical_array_layer; @@ -3721,7 +3809,8 @@ isl_surf_get_uncompressed_surf(const struct isl_device *dev, /* If we ever enable 3D block formats, we'll need to re-think this */ assert(fmtl->bd == 1); - if (isl_tiling_is_std_y(surf->tiling) || surf->tiling == ISL_TILING_64) { + if (isl_tiling_is_std_y(surf->tiling) || + isl_tiling_is_64(surf->tiling)) { /* If the requested level is not part of the miptail, we just offset to * the requested level. Because we're using standard tilings and aren't * in the miptail, arrays and 3D textures should just work so long as we diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index 21bdb61fe22..c3640cd7a2f 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -588,6 +588,8 @@ enum isl_tiling { ISL_TILING_4, /** 64K tiling.*/ ISL_TILING_64, + /** Xe2 64K tiling.*/ + ISL_TILING_64_XE2, /** Tiling format for HiZ surfaces */ ISL_TILING_HIZ, /** Tiling format for CCS surfaces */ @@ -611,6 +613,7 @@ typedef uint32_t isl_tiling_flags_t; #define ISL_TILING_ICL_Ys_BIT (1u << ISL_TILING_ICL_Ys) #define ISL_TILING_4_BIT (1u << ISL_TILING_4) #define ISL_TILING_64_BIT (1u << ISL_TILING_64) +#define ISL_TILING_64_XE2_BIT (1u << ISL_TILING_64_XE2) #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ) #define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS) #define ISL_TILING_GFX12_CCS_BIT (1u << ISL_TILING_GFX12_CCS) @@ -629,6 +632,11 @@ typedef uint32_t isl_tiling_flags_t; ISL_TILING_SKL_Ys_BIT | \ ISL_TILING_ICL_Yf_BIT | \ ISL_TILING_ICL_Ys_BIT) + +/** Any Tiling 64 */ +#define ISL_TILING_STD_64_MASK (ISL_TILING_64_BIT | \ + ISL_TILING_64_XE2_BIT) + /** @} */ /** @@ -2207,6 +2215,12 @@ isl_tiling_is_std_y(enum isl_tiling tiling) return (1u << tiling) & ISL_TILING_STD_Y_MASK; } +static inline bool +isl_tiling_is_64(enum isl_tiling tiling) +{ + return (1u << tiling) & ISL_TILING_STD_64_MASK; +} + uint32_t isl_tiling_to_i915_tiling(enum isl_tiling tiling); diff --git a/src/intel/isl/isl_drm.c b/src/intel/isl/isl_drm.c index d6c6379c437..8b3d10a5d4c 100644 --- a/src/intel/isl/isl_drm.c +++ b/src/intel/isl/isl_drm.c @@ -53,6 +53,7 @@ isl_tiling_to_i915_tiling(enum isl_tiling tiling) case ISL_TILING_ICL_Ys: case ISL_TILING_4: case ISL_TILING_64: + case ISL_TILING_64_XE2: case ISL_TILING_GFX12_CCS: return I915_TILING_NONE; } diff --git a/src/intel/isl/isl_emit_cpb.c b/src/intel/isl/isl_emit_cpb.c index b85f4f57748..e57fa929167 100644 --- a/src/intel/isl/isl_emit_cpb.c +++ b/src/intel/isl/isl_emit_cpb.c @@ -42,7 +42,11 @@ __gen_combine_address(__attribute__((unused)) void *data, #if GFX_VERx10 >= 125 static const uint8_t isl_encode_tiling[] = { [ISL_TILING_4] = TILE4, +#if GFX_VER >= 20 + [ISL_TILING_64_XE2] = TILE64, +#else [ISL_TILING_64] = TILE64, +#endif }; #endif @@ -55,7 +59,7 @@ isl_genX(emit_cpb_control_s)(const struct isl_device *dev, void *batch, assert((info->surf->usage & ISL_SURF_USAGE_CPB_BIT)); assert(info->surf->dim != ISL_SURF_DIM_3D); assert(info->surf->tiling == ISL_TILING_4 || - info->surf->tiling == ISL_TILING_64); + isl_tiling_is_64(info->surf->tiling)); assert(info->surf->format == ISL_FORMAT_R8_UINT); } diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c index a914b8796a3..dc23f5a6474 100644 --- a/src/intel/isl/isl_emit_depth_stencil.c +++ b/src/intel/isl/isl_emit_depth_stencil.c @@ -60,7 +60,10 @@ static const uint32_t isl_encode_ds_surftype[] = { #if GFX_VER >= 9 static const uint8_t isl_encode_tiling[] = { -#if GFX_VERx10 >= 125 +#if GFX_VER >= 20 + [ISL_TILING_4] = TILE4, + [ISL_TILING_64_XE2] = TILE64, +#elif GFX_VERx10 >= 125 [ISL_TILING_4] = TILE4, [ISL_TILING_64] = TILE64, #else diff --git a/src/intel/isl/isl_genX_helpers.h b/src/intel/isl/isl_genX_helpers.h index feb69eaac2e..f9383af4a8b 100644 --- a/src/intel/isl/isl_genX_helpers.h +++ b/src/intel/isl/isl_genX_helpers.h @@ -82,7 +82,7 @@ UNUSED static struct isl_extent3d isl_get_image_alignment(const struct isl_surf *surf) { if (GFX_VERx10 >= 125) { - if (surf->tiling == ISL_TILING_64) { + if (isl_tiling_is_64(surf->tiling)) { /* The hardware ignores the alignment values. Anyway, the surface's * true alignment is likely outside the enum range of HALIGN* and * VALIGN*. diff --git a/src/intel/isl/isl_gfx12.c b/src/intel/isl/isl_gfx12.c index 88a44b49020..c5319788ea5 100644 --- a/src/intel/isl/isl_gfx12.c +++ b/src/intel/isl/isl_gfx12.c @@ -43,13 +43,17 @@ isl_gfx125_filter_tiling(const struct isl_device *dev, { /* Clear flags unsupported on this hardware */ assert(ISL_GFX_VERX10(dev) >= 125); + + const isl_tiling_flags_t tile64_bit = + ISL_GFX_VERX10(dev) >= 200 ? ISL_TILING_64_XE2_BIT : ISL_TILING_64_BIT; + *flags &= ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT | ISL_TILING_4_BIT | - ISL_TILING_64_BIT; + tile64_bit; if (isl_surf_usage_is_depth_or_stencil(info->usage)) { - *flags &= ISL_TILING_4_BIT | ISL_TILING_64_BIT; + *flags &= ISL_TILING_4_BIT | ISL_TILING_STD_64_MASK; /* We choose to avoid Tile64 for 3D depth/stencil buffers. The swizzle * for Tile64 is dependent on the image dimension. So, reads and writes @@ -60,11 +64,11 @@ isl_gfx125_filter_tiling(const struct isl_device *dev, * 3DSTATE_(DEPTH|STENCIL)_BUFFER. */ if (info->dim == ISL_SURF_DIM_3D) - *flags &= ~ISL_TILING_64_BIT; + *flags &= ~ISL_TILING_STD_64_MASK; } if (info->usage & ISL_SURF_USAGE_DISPLAY_BIT) - *flags &= ~ISL_TILING_64_BIT; + *flags &= ~ISL_TILING_STD_64_MASK; /* From RENDER_SURFACE_STATE::AuxiliarySurfaceMode, * @@ -101,13 +105,13 @@ isl_gfx125_filter_tiling(const struct isl_device *dev, * will not support as Tile64" */ if (isl_format_is_yuv(info->format)) - *flags &= ~ISL_TILING_64_BIT; + *flags &= ~ISL_TILING_STD_64_MASK; /* Tile64 tilings for 3D have a different swizzling than a 2D surface. So * filter them out if the usage wants 2D/3D compatibility. */ if (info->usage & ISL_SURF_USAGE_2D_3D_COMPATIBLE_BIT) - *flags &= ~ISL_TILING_64_BIT; + *flags &= ~ISL_TILING_STD_64_MASK; /* From RENDER_SURFACE_STATE::NumberofMultisamples, * @@ -118,11 +122,11 @@ isl_gfx125_filter_tiling(const struct isl_device *dev, * Tile64 is required for multisampling. */ if (info->samples > 1) - *flags &= ISL_TILING_64_BIT; + *flags &= ISL_TILING_STD_64_MASK; /* Tile64 is not defined for format sizes that are 24, 48, and 96 bpb. */ if (isl_format_get_layout(info->format)->bpb % 3 == 0) - *flags &= ~ISL_TILING_64_BIT; + *flags &= ~ISL_TILING_STD_64_MASK; /* BSpec 46962: 3DSTATE_CPSIZE_CONTROL_BUFFER::Tiled Mode : TILE4 & TILE64 * are the only 2 valid values. @@ -131,7 +135,7 @@ isl_gfx125_filter_tiling(const struct isl_device *dev, * additional requirements for TILE4. */ if (info->usage & ISL_SURF_USAGE_CPB_BIT) - *flags &= ISL_TILING_64_BIT; + *flags &= ISL_TILING_STD_64_MASK; } void @@ -147,7 +151,7 @@ isl_gfx125_choose_image_alignment_el(const struct isl_device *dev, const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); - if (tiling == ISL_TILING_64) { + if (isl_tiling_is_64(tiling)) { /* From RENDER_SURFACE_STATE::SurfaceHorizontalAlignment, * * This field is ignored for Tile64 surface formats because horizontal diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index a8f875b50cc..181a3dfd1b4 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -44,7 +44,10 @@ __gen_combine_address(__attribute__((unused)) void *data, static const uint8_t isl_encode_tiling[] = { [ISL_TILING_LINEAR] = LINEAR, [ISL_TILING_X] = XMAJOR, -#if GFX_VERx10 >= 125 +#if GFX_VER >= 20 + [ISL_TILING_4] = TILE4, + [ISL_TILING_64_XE2] = TILE64, +#elif GFX_VERx10 >= 125 [ISL_TILING_4] = TILE4, [ISL_TILING_64] = TILE64, #else diff --git a/src/intel/vulkan/anv_sparse.c b/src/intel/vulkan/anv_sparse.c index 6eb1a4ca642..3d5ef026678 100644 --- a/src/intel/vulkan/anv_sparse.c +++ b/src/intel/vulkan/anv_sparse.c @@ -201,7 +201,7 @@ vk_extent3d_el_to_px(const VkExtent3D extent_el, static bool isl_tiling_supports_standard_block_shapes(enum isl_tiling tiling) { - return tiling == ISL_TILING_64 || + return isl_tiling_is_64(tiling) || tiling == ISL_TILING_ICL_Ys || tiling == ISL_TILING_SKL_Ys; }