mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
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freedreno: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark
parent
3ab072d3c8
commit
c61417e8be
6 changed files with 297 additions and 29 deletions
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@ -11,11 +11,11 @@ The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-04-14 19:13:31)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-04-14 19:13:31)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-04-14 19:14:25)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2017-04-14 19:13:31)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 28504 bytes, from 2017-04-21 20:00:50)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-01 19:45:59)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31541 bytes, from 2017-05-11 17:06:35)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-04-14 19:13:31)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110757 bytes, from 2017-04-14 19:13:31)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 103235 bytes, from 2017-04-21 13:16:50)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 104446 bytes, from 2017-05-12 18:23:03)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-04-14 19:13:30)
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Copyright (C) 2013-2017 by the following authors:
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@ -11,11 +11,11 @@ The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-04-14 19:13:31)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-04-14 19:13:31)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-04-14 19:14:25)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2017-04-14 19:13:31)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 28504 bytes, from 2017-04-21 20:00:50)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-01 19:45:59)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31541 bytes, from 2017-05-11 17:06:35)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-04-14 19:13:31)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110757 bytes, from 2017-04-14 19:13:31)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 103235 bytes, from 2017-04-21 13:16:50)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 104446 bytes, from 2017-05-12 18:23:03)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-04-14 19:13:30)
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Copyright (C) 2013-2017 by the following authors:
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@ -11,11 +11,11 @@ The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-04-14 19:13:31)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-04-14 19:13:31)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-04-14 19:14:25)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2017-04-14 19:13:31)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 28504 bytes, from 2017-04-21 20:00:50)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-01 19:45:59)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31541 bytes, from 2017-05-11 17:06:35)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-04-14 19:13:31)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110757 bytes, from 2017-04-14 19:13:31)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 103235 bytes, from 2017-04-21 13:16:50)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 104446 bytes, from 2017-05-12 18:23:03)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-04-14 19:13:30)
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Copyright (C) 2013-2017 by the following authors:
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@ -11,11 +11,11 @@ The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-04-14 19:13:31)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-04-14 19:13:31)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-04-14 19:14:25)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2017-04-14 19:13:31)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 28504 bytes, from 2017-04-21 20:00:50)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-01 19:45:59)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31541 bytes, from 2017-05-11 17:06:35)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-04-14 19:13:31)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110757 bytes, from 2017-04-14 19:13:31)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 103235 bytes, from 2017-04-21 13:16:50)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 104446 bytes, from 2017-05-12 18:23:03)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-04-14 19:13:30)
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Copyright (C) 2013-2017 by the following authors:
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@ -1341,25 +1341,85 @@ static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
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#define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810
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#define REG_A5XX_VSC_PIPE_DATA_LENGTH_0 0x00000c00
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#define REG_A5XX_VSC_BIN_SIZE 0x00000bc2
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#define A5XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff
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#define A5XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
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static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
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{
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assert(!(val & 0x1f));
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return ((val >> 5) << A5XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A5XX_VSC_BIN_SIZE_WIDTH__MASK;
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}
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#define A5XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001fe00
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#define A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT 9
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static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
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{
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assert(!(val & 0x1f));
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return ((val >> 5) << A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A5XX_VSC_BIN_SIZE_HEIGHT__MASK;
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}
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#define REG_A5XX_VSC_SIZE_ADDRESS_LO 0x00000bc3
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#define REG_A5XX_VSC_SIZE_ADDRESS_HI 0x00000bc4
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#define REG_A5XX_UNKNOWN_0BC5 0x00000bc5
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#define REG_A5XX_UNKNOWN_0BC6 0x00000bc6
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static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
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static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
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#define A5XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
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#define A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
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static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
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{
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return ((val) << A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_X__MASK;
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}
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#define A5XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
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#define A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
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static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
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{
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return ((val) << A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_Y__MASK;
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}
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#define A5XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000
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#define A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
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static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
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{
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return ((val) << A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_W__MASK;
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}
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#define A5XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000
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#define A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24
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static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
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{
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return ((val) << A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_H__MASK;
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}
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static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
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static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
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static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0; }
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static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
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static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
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#define REG_A5XX_VSC_PERFCTR_VSC_SEL_0 0x00000c60
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#define REG_A5XX_VSC_PERFCTR_VSC_SEL_1 0x00000c61
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#define REG_A5XX_VSC_BIN_SIZE 0x00000cdd
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#define A5XX_VSC_BIN_SIZE_WINDOW_OFFSET_DISABLE 0x80000000
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#define A5XX_VSC_BIN_SIZE_X__MASK 0x00007fff
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#define A5XX_VSC_BIN_SIZE_X__SHIFT 0
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static inline uint32_t A5XX_VSC_BIN_SIZE_X(uint32_t val)
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#define REG_A5XX_VSC_RESOLVE_CNTL 0x00000cdd
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#define A5XX_VSC_RESOLVE_CNTL_WINDOW_OFFSET_DISABLE 0x80000000
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#define A5XX_VSC_RESOLVE_CNTL_X__MASK 0x00007fff
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#define A5XX_VSC_RESOLVE_CNTL_X__SHIFT 0
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static inline uint32_t A5XX_VSC_RESOLVE_CNTL_X(uint32_t val)
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{
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return ((val) << A5XX_VSC_BIN_SIZE_X__SHIFT) & A5XX_VSC_BIN_SIZE_X__MASK;
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return ((val) << A5XX_VSC_RESOLVE_CNTL_X__SHIFT) & A5XX_VSC_RESOLVE_CNTL_X__MASK;
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}
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#define A5XX_VSC_BIN_SIZE_Y__MASK 0x7fff0000
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#define A5XX_VSC_BIN_SIZE_Y__SHIFT 16
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static inline uint32_t A5XX_VSC_BIN_SIZE_Y(uint32_t val)
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#define A5XX_VSC_RESOLVE_CNTL_Y__MASK 0x7fff0000
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#define A5XX_VSC_RESOLVE_CNTL_Y__SHIFT 16
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static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
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{
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return ((val) << A5XX_VSC_BIN_SIZE_Y__SHIFT) & A5XX_VSC_BIN_SIZE_Y__MASK;
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return ((val) << A5XX_VSC_RESOLVE_CNTL_Y__SHIFT) & A5XX_VSC_RESOLVE_CNTL_Y__MASK;
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}
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#define REG_A5XX_GRAS_ADDR_MODE_CNTL 0x00000c81
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@ -1522,6 +1582,7 @@ static inline uint32_t A5XX_VSC_BIN_SIZE_Y(uint32_t val)
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#define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61
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#define REG_A5XX_VPC_MODE_CNTL 0x00000e62
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#define A5XX_VPC_MODE_CNTL_BINNING_PASS 0x00000001
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#define REG_A5XX_VPC_PERFCTR_VPC_SEL_0 0x00000e64
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@ -2107,6 +2168,7 @@ static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_dep
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#define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x0000e099
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#define REG_A5XX_GRAS_SC_CNTL 0x0000e0a0
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#define A5XX_GRAS_SC_CNTL_BINNING_PASS 0x00000001
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#define A5XX_GRAS_SC_CNTL_SAMPLES_PASSED 0x00008000
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#define REG_A5XX_GRAS_SC_BIN_CNTL 0x0000e0a1
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@ -2250,7 +2312,9 @@ static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val)
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#define A5XX_RB_CNTL_BYPASS 0x00020000
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#define REG_A5XX_RB_RENDER_CNTL 0x0000e141
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#define A5XX_RB_RENDER_CNTL_BINNING_PASS 0x00000001
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#define A5XX_RB_RENDER_CNTL_SAMPLES_PASSED 0x00000040
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#define A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE 0x00000080
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#define A5XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000
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#define A5XX_RB_RENDER_CNTL_FLAG_DEPTH2 0x00008000
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#define A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000
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@ -11,11 +11,11 @@ The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-04-14 19:13:31)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-04-14 19:13:31)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-04-14 19:14:25)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2017-04-14 19:13:31)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 28504 bytes, from 2017-04-21 20:00:50)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-01 19:45:59)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31541 bytes, from 2017-05-11 17:06:35)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-04-14 19:13:31)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110757 bytes, from 2017-04-14 19:13:31)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 103235 bytes, from 2017-04-21 13:16:50)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 104446 bytes, from 2017-05-12 18:23:03)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-04-14 19:13:30)
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Copyright (C) 2013-2017 by the following authors:
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@ -424,6 +424,35 @@ static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
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#define REG_AXXX_CP_IB2_BUFSZ 0x0000045b
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#define REG_AXXX_CP_STAT 0x0000047f
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#define AXXX_CP_STAT_CP_BUSY 0x80000000
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#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY 0x40000000
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#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY 0x20000000
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#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY 0x10000000
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#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY 0x08000000
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#define AXXX_CP_STAT_ME_BUSY 0x04000000
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#define AXXX_CP_STAT_MIU_WR_C_BUSY 0x02000000
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#define AXXX_CP_STAT_CP_3D_BUSY 0x00800000
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#define AXXX_CP_STAT_CP_NRT_BUSY 0x00400000
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#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY 0x00200000
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#define AXXX_CP_STAT_RCIU_ME_BUSY 0x00100000
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#define AXXX_CP_STAT_RCIU_PFP_BUSY 0x00080000
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#define AXXX_CP_STAT_MEQ_RING_BUSY 0x00040000
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#define AXXX_CP_STAT_PFP_BUSY 0x00020000
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#define AXXX_CP_STAT_ST_QUEUE_BUSY 0x00010000
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#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY 0x00002000
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#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY 0x00001000
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#define AXXX_CP_STAT_RING_QUEUE_BUSY 0x00000800
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#define AXXX_CP_STAT_CSF_BUSY 0x00000400
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#define AXXX_CP_STAT_CSF_ST_BUSY 0x00000200
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#define AXXX_CP_STAT_EVENT_BUSY 0x00000100
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#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY 0x00000080
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#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY 0x00000040
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#define AXXX_CP_STAT_CSF_RING_BUSY 0x00000020
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#define AXXX_CP_STAT_RCIU_BUSY 0x00000010
|
||||
#define AXXX_CP_STAT_RBIU_BUSY 0x00000008
|
||||
#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY 0x00000004
|
||||
#define AXXX_CP_STAT_MIU_RD_REQ_BUSY 0x00000002
|
||||
#define AXXX_CP_STAT_MIU_WR_BUSY 0x00000001
|
||||
|
||||
#define REG_AXXX_CP_SCRATCH_REG0 0x00000578
|
||||
|
||||
|
|
|
|||
|
|
@ -11,11 +11,11 @@ The rules-ng-ng source files this header was generated from are:
|
|||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-04-14 19:13:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-04-14 19:13:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-04-14 19:14:25)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2017-04-14 19:13:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 28504 bytes, from 2017-04-21 20:00:50)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-01 19:45:59)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31541 bytes, from 2017-05-11 17:06:35)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-04-14 19:13:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110757 bytes, from 2017-04-14 19:13:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 103235 bytes, from 2017-04-21 13:16:50)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 104446 bytes, from 2017-05-12 18:23:03)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-04-14 19:13:30)
|
||||
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
|
|
@ -142,11 +142,13 @@ enum adreno_pm4_type3_packets {
|
|||
CP_WAIT_IB_PFD_COMPLETE = 93,
|
||||
CP_REG_RMW = 33,
|
||||
CP_SET_BIN_DATA = 47,
|
||||
CP_SET_BIN_DATA5 = 47,
|
||||
CP_REG_TO_MEM = 62,
|
||||
CP_MEM_WRITE = 61,
|
||||
CP_MEM_WRITE_CNTR = 79,
|
||||
CP_COND_EXEC = 68,
|
||||
CP_COND_WRITE = 69,
|
||||
CP_COND_WRITE5 = 69,
|
||||
CP_EVENT_WRITE = 70,
|
||||
CP_EVENT_WRITE_SHD = 88,
|
||||
CP_EVENT_WRITE_CFL = 89,
|
||||
|
|
@ -282,6 +284,16 @@ enum a4xx_index_size {
|
|||
INDEX4_SIZE_32_BIT = 2,
|
||||
};
|
||||
|
||||
enum cp_cond_function {
|
||||
WRITE_ALWAYS = 0,
|
||||
WRITE_LT = 1,
|
||||
WRITE_LE = 2,
|
||||
WRITE_EQ = 3,
|
||||
WRITE_NE = 4,
|
||||
WRITE_GE = 5,
|
||||
WRITE_GT = 6,
|
||||
};
|
||||
|
||||
enum render_mode_cmd {
|
||||
BYPASS = 1,
|
||||
BINNING = 2,
|
||||
|
|
@ -650,6 +662,52 @@ static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
|
|||
return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_BIN_DATA5_0 0x00000000
|
||||
#define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK 0x003f0000
|
||||
#define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT 16
|
||||
static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK;
|
||||
}
|
||||
#define CP_SET_BIN_DATA5_0_VSC_N__MASK 0x07c00000
|
||||
#define CP_SET_BIN_DATA5_0_VSC_N__SHIFT 22
|
||||
static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_BIN_DATA5_1 0x00000001
|
||||
#define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK 0xffffffff
|
||||
#define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT 0
|
||||
static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_BIN_DATA5_2 0x00000002
|
||||
#define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK 0xffffffff
|
||||
#define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT 0
|
||||
static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_BIN_DATA5_3 0x00000003
|
||||
#define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK 0xffffffff
|
||||
#define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT 0
|
||||
static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_BIN_DATA5_4 0x00000004
|
||||
#define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK 0xffffffff
|
||||
#define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT 0
|
||||
static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_REG_TO_MEM_0 0x00000000
|
||||
#define CP_REG_TO_MEM_0_REG__MASK 0x0000ffff
|
||||
#define CP_REG_TO_MEM_0_REG__SHIFT 0
|
||||
|
|
@ -680,6 +738,122 @@ static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
|
|||
#define CP_MEM_TO_MEM_0_NEG_C 0x00000004
|
||||
#define CP_MEM_TO_MEM_0_DOUBLE 0x20000000
|
||||
|
||||
#define REG_CP_COND_WRITE_0 0x00000000
|
||||
#define CP_COND_WRITE_0_FUNCTION__MASK 0x00000007
|
||||
#define CP_COND_WRITE_0_FUNCTION__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK;
|
||||
}
|
||||
#define CP_COND_WRITE_0_POLL_MEMORY 0x00000010
|
||||
#define CP_COND_WRITE_0_WRITE_MEMORY 0x00000100
|
||||
|
||||
#define REG_CP_COND_WRITE_1 0x00000001
|
||||
#define CP_COND_WRITE_1_POLL_ADDR__MASK 0xffffffff
|
||||
#define CP_COND_WRITE_1_POLL_ADDR__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE_2 0x00000002
|
||||
#define CP_COND_WRITE_2_REF__MASK 0xffffffff
|
||||
#define CP_COND_WRITE_2_REF__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE_3 0x00000003
|
||||
#define CP_COND_WRITE_3_MASK__MASK 0xffffffff
|
||||
#define CP_COND_WRITE_3_MASK__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE_4 0x00000004
|
||||
#define CP_COND_WRITE_4_WRITE_ADDR__MASK 0xffffffff
|
||||
#define CP_COND_WRITE_4_WRITE_ADDR__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE_5 0x00000005
|
||||
#define CP_COND_WRITE_5_WRITE_DATA__MASK 0xffffffff
|
||||
#define CP_COND_WRITE_5_WRITE_DATA__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE5_0 0x00000000
|
||||
#define CP_COND_WRITE5_0_FUNCTION__MASK 0x00000007
|
||||
#define CP_COND_WRITE5_0_FUNCTION__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;
|
||||
}
|
||||
#define CP_COND_WRITE5_0_POLL_MEMORY 0x00000010
|
||||
#define CP_COND_WRITE5_0_WRITE_MEMORY 0x00000100
|
||||
|
||||
#define REG_CP_COND_WRITE5_1 0x00000001
|
||||
#define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK 0xffffffff
|
||||
#define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE5_2 0x00000002
|
||||
#define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK 0xffffffff
|
||||
#define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE5_3 0x00000003
|
||||
#define CP_COND_WRITE5_3_REF__MASK 0xffffffff
|
||||
#define CP_COND_WRITE5_3_REF__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE5_4 0x00000004
|
||||
#define CP_COND_WRITE5_4_MASK__MASK 0xffffffff
|
||||
#define CP_COND_WRITE5_4_MASK__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE5_5 0x00000005
|
||||
#define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK 0xffffffff
|
||||
#define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE5_6 0x00000006
|
||||
#define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK 0xffffffff
|
||||
#define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE5_7 0x00000007
|
||||
#define CP_COND_WRITE5_7_WRITE_DATA__MASK 0xffffffff
|
||||
#define CP_COND_WRITE5_7_WRITE_DATA__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_DISPATCH_COMPUTE_0 0x00000000
|
||||
|
||||
#define REG_CP_DISPATCH_COMPUTE_1 0x00000001
|
||||
|
|
@ -731,6 +905,7 @@ static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)
|
|||
}
|
||||
|
||||
#define REG_CP_SET_RENDER_MODE_3 0x00000003
|
||||
#define CP_SET_RENDER_MODE_3_VSC_ENABLE 0x00000008
|
||||
#define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010
|
||||
|
||||
#define REG_CP_SET_RENDER_MODE_4 0x00000004
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue