diff --git a/src/gallium/drivers/crocus/crocus_context.h b/src/gallium/drivers/crocus/crocus_context.h index 071c6fe4508..2a2c351c65e 100644 --- a/src/gallium/drivers/crocus/crocus_context.h +++ b/src/gallium/drivers/crocus/crocus_context.h @@ -511,7 +511,7 @@ struct crocus_context { struct { struct crocus_uncompiled_shader *uncompiled[MESA_SHADER_STAGES]; struct crocus_compiled_shader *prog[MESA_SHADER_STAGES]; - struct brw_vue_map *last_vue_map; + struct intel_vue_map *last_vue_map; struct crocus_bo *cache_bo; uint32_t cache_next_offset; diff --git a/src/gallium/drivers/crocus/crocus_program.c b/src/gallium/drivers/crocus/crocus_program.c index 5557999456b..2199c7dff4b 100644 --- a/src/gallium/drivers/crocus/crocus_program.c +++ b/src/gallium/drivers/crocus/crocus_program.c @@ -1553,7 +1553,7 @@ crocus_compile_tes(struct crocus_context *ice, if (can_push_ubo(devinfo)) brw_nir_analyze_ubo_ranges(compiler, nir, prog_data->ubo_ranges); - struct brw_vue_map input_vue_map; + struct intel_vue_map input_vue_map; brw_compute_tess_vue_map(&input_vue_map, key->inputs_read, key->patch_inputs_read); @@ -1798,7 +1798,7 @@ static struct crocus_compiled_shader * crocus_compile_fs(struct crocus_context *ice, struct crocus_uncompiled_shader *ish, const struct brw_wm_prog_key *key, - struct brw_vue_map *vue_map) + struct intel_vue_map *vue_map) { struct crocus_screen *screen = (struct crocus_screen *)ice->ctx.screen; const struct brw_compiler *compiler = screen->compiler; @@ -1950,8 +1950,8 @@ update_last_vue_map(struct crocus_context *ice, struct crocus_screen *screen = (struct crocus_screen *)ice->ctx.screen; const struct intel_device_info *devinfo = &screen->devinfo; struct brw_vue_prog_data *vue_prog_data = (void *) prog_data; - struct brw_vue_map *vue_map = &vue_prog_data->vue_map; - struct brw_vue_map *old_map = ice->shaders.last_vue_map; + struct intel_vue_map *vue_map = &vue_prog_data->vue_map; + struct intel_vue_map *old_map = ice->shaders.last_vue_map; const uint64_t changed_slots = (old_map ? old_map->slots_valid : 0ull) ^ vue_map->slots_valid; @@ -2872,7 +2872,7 @@ crocus_create_fs_state(struct pipe_context *ctx, can_rearrange_varyings ? 0 : info->inputs_read | VARYING_BIT_POS, }; - struct brw_vue_map vue_map; + struct intel_vue_map vue_map; if (devinfo->ver < 6) { brw_compute_vue_map(devinfo, &vue_map, info->inputs_read | VARYING_BIT_POS, diff --git a/src/gallium/drivers/crocus/crocus_screen.h b/src/gallium/drivers/crocus/crocus_screen.h index d60abcb3f34..865c8898a19 100644 --- a/src/gallium/drivers/crocus/crocus_screen.h +++ b/src/gallium/drivers/crocus/crocus_screen.h @@ -37,7 +37,7 @@ struct crocus_resource; struct crocus_context; struct crocus_sampler_state; -struct brw_vue_map; +struct intel_vue_map; struct brw_tcs_prog_key; struct brw_tes_prog_key; struct brw_cs_prog_key; @@ -115,7 +115,7 @@ struct crocus_vtable { uint32_t report_id); uint32_t *(*create_so_decl_list)(const struct pipe_stream_output_info *sol, - const struct brw_vue_map *vue_map); + const struct intel_vue_map *vue_map); void (*populate_vs_key)(const struct crocus_context *ice, const struct shader_info *info, gl_shader_stage last_stage, diff --git a/src/gallium/drivers/crocus/crocus_state.c b/src/gallium/drivers/crocus/crocus_state.c index e13159a2af1..0b4e23b8385 100644 --- a/src/gallium/drivers/crocus/crocus_state.c +++ b/src/gallium/drivers/crocus/crocus_state.c @@ -4267,7 +4267,7 @@ crocus_set_stream_output_targets(struct pipe_context *ctx, */ static uint32_t * crocus_create_so_decl_list(const struct pipe_stream_output_info *info, - const struct brw_vue_map *vue_map) + const struct intel_vue_map *vue_map) { struct GENX(SO_DECL) so_decl[PIPE_MAX_VERTEX_STREAMS][128]; int buffer_mask[PIPE_MAX_VERTEX_STREAMS] = {0, 0, 0, 0}; @@ -4453,7 +4453,7 @@ crocus_is_drawing_points(const struct crocus_context *ice) static void get_attr_override( struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL) *attr, - const struct brw_vue_map *vue_map, + const struct intel_vue_map *vue_map, int urb_entry_read_offset, int fs_attr, bool two_side_color, uint32_t *max_source_attr) { @@ -4554,7 +4554,7 @@ calculate_attr_overrides( { const struct brw_wm_prog_data *wm_prog_data = (void *) ice->shaders.prog[MESA_SHADER_FRAGMENT]->prog_data; - const struct brw_vue_map *vue_map = ice->shaders.last_vue_map; + const struct intel_vue_map *vue_map = ice->shaders.last_vue_map; const struct crocus_rasterizer_state *cso_rast = ice->state.cso_rast; uint32_t max_source_attr = 0; const struct shader_info *fs_info = diff --git a/src/gallium/drivers/iris/iris_program.c b/src/gallium/drivers/iris/iris_program.c index 62ae340f315..81c0fdc0205 100644 --- a/src/gallium/drivers/iris/iris_program.c +++ b/src/gallium/drivers/iris/iris_program.c @@ -1665,7 +1665,7 @@ iris_compile_tes(struct iris_screen *screen, brw_nir_analyze_ubo_ranges(compiler, nir, prog_data->ubo_ranges); - struct brw_vue_map input_vue_map; + struct intel_vue_map input_vue_map; brw_compute_tess_vue_map(&input_vue_map, key->inputs_read, key->patch_inputs_read); @@ -1912,7 +1912,7 @@ iris_compile_fs(struct iris_screen *screen, struct util_debug_callback *dbg, struct iris_uncompiled_shader *ish, struct iris_compiled_shader *shader, - struct brw_vue_map *vue_map) + struct intel_vue_map *vue_map) { const struct brw_compiler *compiler = screen->compiler; void *mem_ctx = ralloc_context(NULL); @@ -2011,7 +2011,7 @@ iris_update_compiled_fs(struct iris_context *ice) struct iris_fs_prog_key key = { KEY_INIT(base) }; screen->vtbl.populate_fs_key(ice, &ish->nir->info, &key); - struct brw_vue_map *last_vue_map = + struct intel_vue_map *last_vue_map = &brw_vue_prog_data(ice->shaders.last_vue_shader->prog_data)->vue_map; if (ish->nos & (1ull << IRIS_NOS_LAST_VUE_MAP)) @@ -2057,8 +2057,8 @@ update_last_vue_map(struct iris_context *ice, struct iris_compiled_shader *shader) { struct brw_vue_prog_data *vue_prog_data = (void *) shader->prog_data; - struct brw_vue_map *vue_map = &vue_prog_data->vue_map; - struct brw_vue_map *old_map = !ice->shaders.last_vue_shader ? NULL : + struct intel_vue_map *vue_map = &vue_prog_data->vue_map; + struct intel_vue_map *old_map = !ice->shaders.last_vue_shader ? NULL : &brw_vue_prog_data(ice->shaders.last_vue_shader->prog_data)->vue_map; const uint64_t changed_slots = (old_map ? old_map->slots_valid : 0ull) ^ vue_map->slots_valid; diff --git a/src/gallium/drivers/iris/iris_screen.h b/src/gallium/drivers/iris/iris_screen.h index 3e234dcc68b..a41b14ee6a0 100644 --- a/src/gallium/drivers/iris/iris_screen.h +++ b/src/gallium/drivers/iris/iris_screen.h @@ -36,7 +36,7 @@ #include "iris_resource.h" struct intel_l3_config; -struct brw_vue_map; +struct intel_vue_map; struct iris_vs_prog_key; struct iris_tcs_prog_key; struct iris_tes_prog_key; @@ -136,7 +136,7 @@ struct iris_vtable { enum iris_program_cache_id cache_id, struct iris_compiled_shader *shader); uint32_t *(*create_so_decl_list)(const struct pipe_stream_output_info *sol, - const struct brw_vue_map *vue_map); + const struct intel_vue_map *vue_map); void (*populate_vs_key)(const struct iris_context *ice, const struct shader_info *info, gl_shader_stage last_stage, diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 77ad2501ed7..51e8962c3b6 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -4437,7 +4437,7 @@ iris_set_stream_output_targets(struct pipe_context *ctx, */ static uint32_t * iris_create_so_decl_list(const struct pipe_stream_output_info *info, - const struct brw_vue_map *vue_map) + const struct intel_vue_map *vue_map) { struct GENX(SO_DECL) so_decl[PIPE_MAX_VERTEX_STREAMS][128]; int buffer_mask[PIPE_MAX_VERTEX_STREAMS] = {0, 0, 0, 0}; @@ -4551,7 +4551,7 @@ iris_create_so_decl_list(const struct pipe_stream_output_info *info, static void iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots, - const struct brw_vue_map *last_vue_map, + const struct intel_vue_map *last_vue_map, bool two_sided_color, unsigned *out_offset, unsigned *out_length) @@ -4621,7 +4621,7 @@ iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots, static void iris_emit_sbe_swiz(struct iris_batch *batch, const struct iris_context *ice, - const struct brw_vue_map *vue_map, + const struct intel_vue_map *vue_map, unsigned urb_read_offset, unsigned sprite_coord_enables) { @@ -4755,7 +4755,7 @@ iris_emit_sbe(struct iris_batch *batch, const struct iris_context *ice) const struct iris_rasterizer_state *cso_rast = ice->state.cso_rast; const struct brw_wm_prog_data *wm_prog_data = (void *) ice->shaders.prog[MESA_SHADER_FRAGMENT]->prog_data; - const struct brw_vue_map *last_vue_map = + const struct intel_vue_map *last_vue_map = &brw_vue_prog_data(ice->shaders.last_vue_shader->prog_data)->vue_map; unsigned urb_read_offset, urb_read_length; @@ -7138,7 +7138,7 @@ iris_upload_dirty_render_state(struct iris_context *ice, #if INTEL_WA_14015055625_GFX_VER /* Check if FS stage will use primitive ID overrides for Wa_14015055625. */ - const struct brw_vue_map *last_vue_map = + const struct intel_vue_map *last_vue_map = &brw_vue_prog_data(ice->shaders.last_vue_shader->prog_data)->vue_map; if ((wm_prog_data->inputs & VARYING_BIT_PRIMITIVE_ID) && last_vue_map->varying_to_slot[VARYING_SLOT_PRIMITIVE_ID] == -1 && diff --git a/src/intel/blorp/blorp.c b/src/intel/blorp/blorp.c index 716056e5f0f..81ed1d9650a 100644 --- a/src/intel/blorp/blorp.c +++ b/src/intel/blorp/blorp.c @@ -452,7 +452,7 @@ blorp_ensure_sf_program(struct blorp_batch *batch, const unsigned *program; unsigned program_size; - struct brw_vue_map vue_map; + struct intel_vue_map vue_map; brw_compute_vue_map(blorp->compiler->devinfo, &vue_map, slots_valid, false, 1); struct brw_sf_prog_data prog_data_tmp; diff --git a/src/intel/compiler/brw_clip.h b/src/intel/compiler/brw_clip.h index bdf7ee25848..4ca89455963 100644 --- a/src/intel/compiler/brw_clip.h +++ b/src/intel/compiler/brw_clip.h @@ -96,7 +96,7 @@ struct brw_clip_compile { bool need_direction; - struct brw_vue_map vue_map; + struct intel_vue_map vue_map; }; /** diff --git a/src/intel/compiler/brw_compile_clip.c b/src/intel/compiler/brw_compile_clip.c index 3ee26de00e4..843b5ee027a 100644 --- a/src/intel/compiler/brw_compile_clip.c +++ b/src/intel/compiler/brw_compile_clip.c @@ -30,7 +30,7 @@ brw_compile_clip(const struct brw_compiler *compiler, void *mem_ctx, const struct brw_clip_prog_key *key, struct brw_clip_prog_data *prog_data, - struct brw_vue_map *vue_map, + struct intel_vue_map *vue_map, unsigned *final_assembly_size) { struct brw_clip_compile c; diff --git a/src/intel/compiler/brw_compile_ff_gs.c b/src/intel/compiler/brw_compile_ff_gs.c index 57c63f35576..8a1e32d8d0d 100644 --- a/src/intel/compiler/brw_compile_ff_gs.c +++ b/src/intel/compiler/brw_compile_ff_gs.c @@ -66,7 +66,7 @@ struct brw_ff_gs_compile { /* Number of registers used to store vertex data */ GLuint nr_regs; - struct brw_vue_map vue_map; + struct intel_vue_map vue_map; }; /** @@ -563,7 +563,7 @@ brw_compile_ff_gs_prog(struct brw_compiler *compiler, void *mem_ctx, const struct brw_ff_gs_prog_key *key, struct brw_ff_gs_prog_data *prog_data, - struct brw_vue_map *vue_map, + struct intel_vue_map *vue_map, unsigned *final_assembly_size) { struct brw_ff_gs_compile c; diff --git a/src/intel/compiler/brw_compile_sf.c b/src/intel/compiler/brw_compile_sf.c index 94f95aaaf3a..3aed8181fd8 100644 --- a/src/intel/compiler/brw_compile_sf.c +++ b/src/intel/compiler/brw_compile_sf.c @@ -67,7 +67,7 @@ struct brw_sf_compile { /** The last known value of the f0.0 flag register. */ unsigned flag_value; - struct brw_vue_map vue_map; + struct intel_vue_map vue_map; }; /** @@ -805,7 +805,7 @@ brw_compile_sf(const struct brw_compiler *compiler, void *mem_ctx, const struct brw_sf_prog_key *key, struct brw_sf_prog_data *prog_data, - struct brw_vue_map *vue_map, + struct intel_vue_map *vue_map, unsigned *final_assembly_size) { struct brw_sf_compile c; diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h index e5cb497ca1a..fde631ba2d6 100644 --- a/src/intel/compiler/brw_compiler.h +++ b/src/intel/compiler/brw_compiler.h @@ -1368,78 +1368,7 @@ typedef enum (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \ ~VARYING_BIT_POS & ~VARYING_BIT_FACE) -/** - * Data structure recording the relationship between the gl_varying_slot enum - * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a - * single octaword within the VUE (128 bits). - * - * Note that each BRW register contains 256 bits (2 octawords), so when - * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two - * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as - * in a vertex shader), each register corresponds to a single VUE slot, since - * it contains data for two separate vertices. - */ -struct brw_vue_map { - /** - * Bitfield representing all varying slots that are (a) stored in this VUE - * map, and (b) actually written by the shader. Does not include any of - * the additional varying slots defined in brw_varying_slot. - */ - uint64_t slots_valid; - - /** - * Is this VUE map for a separate shader pipeline? - * - * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched - * without the linker having a chance to dead code eliminate unused varyings. - * - * This means that we have to use a fixed slot layout, based on the output's - * location field, rather than assigning slots in a compact contiguous block. - */ - bool separate; - - /** - * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are - * not stored in a slot (because they are not written, or because - * additional processing is applied before storing them in the VUE), the - * value is -1. - */ - signed char varying_to_slot[VARYING_SLOT_TESS_MAX]; - - /** - * Map from VUE slot to gl_varying_slot value. For slots that do not - * directly correspond to a gl_varying_slot, the value comes from - * brw_varying_slot. - * - * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD. - */ - signed char slot_to_varying[VARYING_SLOT_TESS_MAX]; - - /** - * Total number of VUE slots in use - */ - int num_slots; - - /** - * Number of position VUE slots. If num_pos_slots > 1, primitive - * replication is being used. - */ - int num_pos_slots; - - /** - * Number of per-patch VUE slots. Only valid for tessellation control - * shader outputs and tessellation evaluation shader inputs. - */ - int num_per_patch_slots; - - /** - * Number of per-vertex VUE slots. Only valid for tessellation control - * shader outputs and tessellation evaluation shader inputs. - */ - int num_per_vertex_slots; -}; - -void brw_print_vue_map(FILE *fp, const struct brw_vue_map *vue_map, +void brw_print_vue_map(FILE *fp, const struct intel_vue_map *vue_map, gl_shader_stage stage); /** @@ -1455,29 +1384,29 @@ static inline unsigned brw_vue_slot_to_offset(unsigned slot) * VUE. */ static inline unsigned -brw_varying_to_offset(const struct brw_vue_map *vue_map, unsigned varying) +brw_varying_to_offset(const struct intel_vue_map *vue_map, unsigned varying) { return brw_vue_slot_to_offset(vue_map->varying_to_slot[varying]); } void brw_compute_vue_map(const struct intel_device_info *devinfo, - struct brw_vue_map *vue_map, + struct intel_vue_map *vue_map, uint64_t slots_valid, bool separate_shader, uint32_t pos_slots); -void brw_compute_tess_vue_map(struct brw_vue_map *const vue_map, +void brw_compute_tess_vue_map(struct intel_vue_map *const vue_map, uint64_t slots_valid, uint32_t is_patch); /* brw_interpolation_map.c */ -void brw_setup_vue_interpolation(const struct brw_vue_map *vue_map, +void brw_setup_vue_interpolation(const struct intel_vue_map *vue_map, struct nir_shader *nir, struct brw_wm_prog_data *prog_data); struct brw_vue_prog_data { struct brw_stage_prog_data base; - struct brw_vue_map vue_map; + struct intel_vue_map vue_map; /** Should the hardware deliver input VUE handles for URB pull loads? */ bool include_vue_handles; @@ -1831,7 +1760,7 @@ struct brw_compile_tes_params { const struct brw_tes_prog_key *key; struct brw_tes_prog_data *prog_data; - const struct brw_vue_map *input_vue_map; + const struct intel_vue_map *input_vue_map; }; /** @@ -1877,7 +1806,7 @@ brw_compile_sf(const struct brw_compiler *compiler, void *mem_ctx, const struct brw_sf_prog_key *key, struct brw_sf_prog_data *prog_data, - struct brw_vue_map *vue_map, + struct intel_vue_map *vue_map, unsigned *final_assembly_size); /** @@ -1893,7 +1822,7 @@ brw_compile_clip(const struct brw_compiler *compiler, void *mem_ctx, const struct brw_clip_prog_key *key, struct brw_clip_prog_data *prog_data, - struct brw_vue_map *vue_map, + struct intel_vue_map *vue_map, unsigned *final_assembly_size); struct brw_compile_task_params { @@ -1930,7 +1859,7 @@ struct brw_compile_fs_params { const struct brw_wm_prog_key *key; struct brw_wm_prog_data *prog_data; - const struct brw_vue_map *vue_map; + const struct intel_vue_map *vue_map; const struct brw_mue_map *mue_map; bool allow_spilling; @@ -2002,7 +1931,7 @@ brw_compile_ff_gs_prog(struct brw_compiler *compiler, void *mem_ctx, const struct brw_ff_gs_prog_key *key, struct brw_ff_gs_prog_data *prog_data, - struct brw_vue_map *vue_map, + struct intel_vue_map *vue_map, unsigned *final_assembly_size); void brw_debug_key_recompile(const struct brw_compiler *c, void *log, @@ -2158,7 +2087,7 @@ brw_stage_has_packed_dispatch(ASSERTED const struct intel_device_info *devinfo, */ static inline int brw_compute_first_urb_slot_required(uint64_t inputs_read, - const struct brw_vue_map *prev_stage_vue_map) + const struct intel_vue_map *prev_stage_vue_map) { if ((inputs_read & (VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT | VARYING_BIT_PRIMITIVE_SHADING_RATE)) == 0) { for (int i = 0; i < prev_stage_vue_map->num_slots; i++) { diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 244a4fca03b..fd6b6e8e07f 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -1712,7 +1712,7 @@ calculate_urb_setup(const struct intel_device_info *devinfo, * geometry has more than one position slot (used for Primitive * Replication). */ - struct brw_vue_map prev_stage_vue_map; + struct intel_vue_map prev_stage_vue_map; brw_compute_vue_map(devinfo, &prev_stage_vue_map, key->input_slots_valid, nir->info.separate_shader, 1); diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visitor.cpp index 74e7a160fca..9f7f1befd83 100644 --- a/src/intel/compiler/brw_fs_visitor.cpp +++ b/src/intel/compiler/brw_fs_visitor.cpp @@ -829,7 +829,7 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count) (const struct brw_vs_prog_key *) this->key; const GLbitfield64 psiz_mask = VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT | VARYING_BIT_PSIZ | VARYING_BIT_PRIMITIVE_SHADING_RATE; - const struct brw_vue_map *vue_map = &vue_prog_data->vue_map; + const struct intel_vue_map *vue_map = &vue_prog_data->vue_map; bool flush; fs_reg sources[8]; fs_reg urb_handle; diff --git a/src/intel/compiler/brw_interpolation_map.c b/src/intel/compiler/brw_interpolation_map.c index a1e3170e668..bdda1ad5d48 100644 --- a/src/intel/compiler/brw_interpolation_map.c +++ b/src/intel/compiler/brw_interpolation_map.c @@ -37,7 +37,7 @@ static char const *get_qual_name(int mode) static void gfx4_frag_prog_set_interp_modes(struct brw_wm_prog_data *prog_data, - const struct brw_vue_map *vue_map, + const struct intel_vue_map *vue_map, unsigned location, unsigned slot_count, enum glsl_interp_mode interp) { @@ -57,7 +57,7 @@ gfx4_frag_prog_set_interp_modes(struct brw_wm_prog_data *prog_data, /* Set up interpolation modes for every element in the VUE */ void -brw_setup_vue_interpolation(const struct brw_vue_map *vue_map, nir_shader *nir, +brw_setup_vue_interpolation(const struct intel_vue_map *vue_map, nir_shader *nir, struct brw_wm_prog_data *prog_data) { /* Initialise interp_mode. INTERP_MODE_NONE == 0 */ diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 4512241b517..acf71586348 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -183,7 +183,7 @@ is_output(nir_intrinsic_instr *intrin) static bool remap_patch_urb_offsets(nir_block *block, nir_builder *b, - const struct brw_vue_map *vue_map, + const struct intel_vue_map *vue_map, enum tess_primitive_mode tes_primitive_mode) { nir_foreach_instr_safe(instr, block) { @@ -366,7 +366,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir, void brw_nir_lower_vue_inputs(nir_shader *nir, - const struct brw_vue_map *vue_map) + const struct intel_vue_map *vue_map) { nir_foreach_shader_in_variable(var, nir) var->data.driver_location = var->data.location; @@ -415,7 +415,7 @@ brw_nir_lower_vue_inputs(nir_shader *nir, } void -brw_nir_lower_tes_inputs(nir_shader *nir, const struct brw_vue_map *vue_map) +brw_nir_lower_tes_inputs(nir_shader *nir, const struct intel_vue_map *vue_map) { nir_foreach_shader_in_variable(var, nir) var->data.driver_location = var->data.location; @@ -558,7 +558,7 @@ brw_nir_lower_vue_outputs(nir_shader *nir) } void -brw_nir_lower_tcs_outputs(nir_shader *nir, const struct brw_vue_map *vue_map, +brw_nir_lower_tcs_outputs(nir_shader *nir, const struct intel_vue_map *vue_map, enum tess_primitive_mode tes_primitive_mode) { nir_foreach_shader_out_variable(var, nir) { diff --git a/src/intel/compiler/brw_nir.h b/src/intel/compiler/brw_nir.h index 317c8e9c779..aa168bcdfec 100644 --- a/src/intel/compiler/brw_nir.h +++ b/src/intel/compiler/brw_nir.h @@ -182,13 +182,13 @@ void brw_nir_lower_vs_inputs(nir_shader *nir, bool edgeflag_is_last, const uint8_t *vs_attrib_wa_flags); void brw_nir_lower_vue_inputs(nir_shader *nir, - const struct brw_vue_map *vue_map); -void brw_nir_lower_tes_inputs(nir_shader *nir, const struct brw_vue_map *vue); + const struct intel_vue_map *vue_map); +void brw_nir_lower_tes_inputs(nir_shader *nir, const struct intel_vue_map *vue); void brw_nir_lower_fs_inputs(nir_shader *nir, const struct intel_device_info *devinfo, const struct brw_wm_prog_key *key); void brw_nir_lower_vue_outputs(nir_shader *nir); -void brw_nir_lower_tcs_outputs(nir_shader *nir, const struct brw_vue_map *vue, +void brw_nir_lower_tcs_outputs(nir_shader *nir, const struct intel_vue_map *vue, enum tess_primitive_mode tes_primitive_mode); void brw_nir_lower_fs_outputs(nir_shader *nir); diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index ccc64af41a1..7b38b6f4235 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -1285,7 +1285,7 @@ brw_compile_tes(const struct brw_compiler *compiler, const struct intel_device_info *devinfo = compiler->devinfo; nir_shader *nir = params->base.nir; const struct brw_tes_prog_key *key = params->key; - const struct brw_vue_map *input_vue_map = params->input_vue_map; + const struct intel_vue_map *input_vue_map = params->input_vue_map; struct brw_tes_prog_data *prog_data = params->prog_data; const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL]; diff --git a/src/intel/compiler/brw_shader.h b/src/intel/compiler/brw_shader.h index 6fd850093ef..85a1912ee3c 100644 --- a/src/intel/compiler/brw_shader.h +++ b/src/intel/compiler/brw_shader.h @@ -183,7 +183,7 @@ bool brw_texture_offset(const nir_tex_instr *tex, unsigned src, struct brw_gs_compile { struct brw_gs_prog_key key; - struct brw_vue_map input_vue_map; + struct intel_vue_map input_vue_map; unsigned control_data_bits_per_vertex; unsigned control_data_header_size_bits; diff --git a/src/intel/compiler/brw_vec4_tcs.cpp b/src/intel/compiler/brw_vec4_tcs.cpp index 97bb8792e5a..0a2bacb2d0f 100644 --- a/src/intel/compiler/brw_vec4_tcs.cpp +++ b/src/intel/compiler/brw_vec4_tcs.cpp @@ -371,7 +371,7 @@ brw_compile_tcs(const struct brw_compiler *compiler, nir->info.outputs_written = key->outputs_written; nir->info.patch_outputs_written = key->patch_outputs_written; - struct brw_vue_map input_vue_map; + struct intel_vue_map input_vue_map; brw_compute_vue_map(devinfo, &input_vue_map, nir->info.inputs_read, nir->info.separate_shader, 1); brw_compute_tess_vue_map(&vue_prog_data->vue_map, diff --git a/src/intel/compiler/brw_vue_map.c b/src/intel/compiler/brw_vue_map.c index c11708b9df1..56cb560f1e4 100644 --- a/src/intel/compiler/brw_vue_map.c +++ b/src/intel/compiler/brw_vue_map.c @@ -44,7 +44,7 @@ #include "dev/intel_debug.h" static inline void -assign_vue_slot(struct brw_vue_map *vue_map, int varying, int slot) +assign_vue_slot(struct intel_vue_map *vue_map, int varying, int slot) { /* Make sure this varying hasn't been assigned a slot already */ assert (vue_map->varying_to_slot[varying] == -1); @@ -58,7 +58,7 @@ assign_vue_slot(struct brw_vue_map *vue_map, int varying, int slot) */ void brw_compute_vue_map(const struct intel_device_info *devinfo, - struct brw_vue_map *vue_map, + struct intel_vue_map *vue_map, uint64_t slots_valid, bool separate, uint32_t pos_slots) @@ -216,7 +216,7 @@ brw_compute_vue_map(const struct intel_device_info *devinfo, * tessellation evaluation shader inputs. */ void -brw_compute_tess_vue_map(struct brw_vue_map *vue_map, +brw_compute_tess_vue_map(struct intel_vue_map *vue_map, uint64_t vertex_slots, uint32_t patch_slots) { @@ -298,7 +298,7 @@ varying_name(brw_varying_slot slot, gl_shader_stage stage) } void -brw_print_vue_map(FILE *fp, const struct brw_vue_map *vue_map, +brw_print_vue_map(FILE *fp, const struct intel_vue_map *vue_map, gl_shader_stage stage) { if (vue_map->num_per_vertex_slots > 0 || vue_map->num_per_patch_slots > 0) { diff --git a/src/intel/compiler/intel_shader_enums.h b/src/intel/compiler/intel_shader_enums.h index 58a7c2f90ae..621f95febd2 100644 --- a/src/intel/compiler/intel_shader_enums.h +++ b/src/intel/compiler/intel_shader_enums.h @@ -6,6 +6,9 @@ #ifndef INTEL_SHADER_ENUMS_H #define INTEL_SHADER_ENUMS_H +#include + +#include "compiler/shader_enums.h" #include "util/enum_operators.h" #ifdef __cplusplus @@ -86,6 +89,77 @@ enum intel_shader_dispatch_mode { INTEL_DISPATCH_MODE_TCS_MULTI_PATCH = 2, }; +/** + * Data structure recording the relationship between the gl_varying_slot enum + * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a + * single octaword within the VUE (128 bits). + * + * Note that each BRW register contains 256 bits (2 octawords), so when + * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two + * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as + * in a vertex shader), each register corresponds to a single VUE slot, since + * it contains data for two separate vertices. + */ +struct intel_vue_map { + /** + * Bitfield representing all varying slots that are (a) stored in this VUE + * map, and (b) actually written by the shader. Does not include any of + * the additional varying slots defined in brw_varying_slot. + */ + uint64_t slots_valid; + + /** + * Is this VUE map for a separate shader pipeline? + * + * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched + * without the linker having a chance to dead code eliminate unused varyings. + * + * This means that we have to use a fixed slot layout, based on the output's + * location field, rather than assigning slots in a compact contiguous block. + */ + bool separate; + + /** + * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are + * not stored in a slot (because they are not written, or because + * additional processing is applied before storing them in the VUE), the + * value is -1. + */ + signed char varying_to_slot[VARYING_SLOT_TESS_MAX]; + + /** + * Map from VUE slot to gl_varying_slot value. For slots that do not + * directly correspond to a gl_varying_slot, the value comes from + * brw_varying_slot. + * + * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD. + */ + signed char slot_to_varying[VARYING_SLOT_TESS_MAX]; + + /** + * Total number of VUE slots in use + */ + int num_slots; + + /** + * Number of position VUE slots. If num_pos_slots > 1, primitive + * replication is being used. + */ + int num_pos_slots; + + /** + * Number of per-patch VUE slots. Only valid for tessellation control + * shader outputs and tessellation evaluation shader inputs. + */ + int num_per_patch_slots; + + /** + * Number of per-vertex VUE slots. Only valid for tessellation control + * shader outputs and tessellation evaluation shader inputs. + */ + int num_per_vertex_slots; +}; + #ifdef __cplusplus } /* extern "C" */ #endif diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index e6c35fff192..2220e5eb89d 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -1558,7 +1558,7 @@ anv_pipeline_compile_fs(const struct brw_compiler *compiler, fs_stage->key.wm.input_slots_valid = prev_stage->prog_data.vue.vue_map.slots_valid; } else { - struct brw_vue_map prev_vue_map; + struct intel_vue_map prev_vue_map; brw_compute_vue_map(compiler->devinfo, &prev_vue_map, fs_stage->nir->info.inputs_read, diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index 0a806fbe8b8..f33bbde7a59 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -543,7 +543,7 @@ emit_3dstate_sbe(struct anv_graphics_pipeline *pipeline) sbe.AttributeActiveComponentFormat[i] = ACF_XYZW; if (anv_pipeline_is_primitive(pipeline)) { - const struct brw_vue_map *fs_input_map = + const struct intel_vue_map *fs_input_map = &anv_pipeline_get_last_vue_prog_data(pipeline)->vue_map; int first_slot = @@ -988,7 +988,7 @@ emit_3dstate_streamout(struct anv_graphics_pipeline *pipeline, { const struct brw_vue_prog_data *prog_data = anv_pipeline_get_last_vue_prog_data(pipeline); - const struct brw_vue_map *vue_map = &prog_data->vue_map; + const struct intel_vue_map *vue_map = &prog_data->vue_map; nir_xfb_info *xfb_info; if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) diff --git a/src/intel/vulkan_hasvk/genX_pipeline.c b/src/intel/vulkan_hasvk/genX_pipeline.c index cd9785711f0..de752335f56 100644 --- a/src/intel/vulkan_hasvk/genX_pipeline.c +++ b/src/intel/vulkan_hasvk/genX_pipeline.c @@ -362,7 +362,7 @@ emit_3dstate_sbe(struct anv_graphics_pipeline *pipeline) # define swiz sbe #endif - const struct brw_vue_map *fs_input_map = + const struct intel_vue_map *fs_input_map = &anv_pipeline_get_last_vue_prog_data(pipeline)->vue_map; int first_slot = brw_compute_first_urb_slot_required(wm_prog_data->inputs, @@ -1092,7 +1092,7 @@ emit_3dstate_streamout(struct anv_graphics_pipeline *pipeline, { const struct brw_vue_prog_data *prog_data = anv_pipeline_get_last_vue_prog_data(pipeline); - const struct brw_vue_map *vue_map = &prog_data->vue_map; + const struct intel_vue_map *vue_map = &prog_data->vue_map; nir_xfb_info *xfb_info; if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))