From c5a565d094956c769ed30cd5df004d418af779ea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Mon, 5 Jun 2023 15:01:29 -0400 Subject: [PATCH] radeonsi: don't do PFP_SYNC_ME before CP DMA and compute blits It's not needed before them, and we already set it after them. Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_compute_blit.c | 3 --- src/gallium/drivers/radeonsi/si_cp_dma.c | 12 ++++++------ 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_compute_blit.c b/src/gallium/drivers/radeonsi/si_compute_blit.c index f9b3bd09dc3..983ceea335b 100644 --- a/src/gallium/drivers/radeonsi/si_compute_blit.c +++ b/src/gallium/drivers/radeonsi/si_compute_blit.c @@ -152,9 +152,6 @@ static void si_launch_grid_internal(struct si_context *sctx, const struct pipe_g if (flags & SI_OP_SYNC_CS_BEFORE) sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH; - if (!(flags & SI_OP_CS_IMAGE)) - sctx->flags |= SI_CONTEXT_PFP_SYNC_ME; - /* Invalidate L0-L1 caches. */ /* sL0 is never invalidated, because src resources don't use it. */ if (!(flags & SI_OP_SKIP_CACHE_INV_BEFORE)) diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c index 30d8fc1c955..fa605d4234f 100644 --- a/src/gallium/drivers/radeonsi/si_cp_dma.c +++ b/src/gallium/drivers/radeonsi/si_cp_dma.c @@ -180,13 +180,13 @@ void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs, assert(size && size % 4 == 0); if (user_flags & SI_OP_SYNC_GE_BEFORE) - sctx->flags |= SI_CONTEXT_VS_PARTIAL_FLUSH | SI_CONTEXT_PFP_SYNC_ME; + sctx->flags |= SI_CONTEXT_VS_PARTIAL_FLUSH; if (user_flags & SI_OP_SYNC_CS_BEFORE) - sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH | SI_CONTEXT_PFP_SYNC_ME; + sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH; if (user_flags & SI_OP_SYNC_PS_BEFORE) - sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_PFP_SYNC_ME; + sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH; /* Mark the buffer range of destination as valid (initialized), * so that transfer_map knows it should wait for the GPU when mapping @@ -325,13 +325,13 @@ void si_cp_dma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst, } if (user_flags & SI_OP_SYNC_GE_BEFORE) - sctx->flags |= SI_CONTEXT_VS_PARTIAL_FLUSH | SI_CONTEXT_PFP_SYNC_ME; + sctx->flags |= SI_CONTEXT_VS_PARTIAL_FLUSH; if (user_flags & SI_OP_SYNC_CS_BEFORE) - sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH | SI_CONTEXT_PFP_SYNC_ME; + sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH; if (user_flags & SI_OP_SYNC_PS_BEFORE) - sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_PFP_SYNC_ME; + sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH; if ((dst || src) && !(user_flags & SI_OP_SKIP_CACHE_INV_BEFORE)) sctx->flags |= si_get_flush_flags(sctx, coher, cache_policy);