diff --git a/src/amd/common/ac_cmdbuf.h b/src/amd/common/ac_cmdbuf.h index f8529d439c8..23b1c7c6c8d 100644 --- a/src/amd/common/ac_cmdbuf.h +++ b/src/amd/common/ac_cmdbuf.h @@ -22,6 +22,8 @@ struct ac_cmdbuf { uint32_t max_dw; /* Maximum number of dwords. */ uint32_t reserved_dw; /* Number of dwords reserved. */ uint32_t *buf; /* The base pointer of the chunk. */ + + bool context_roll; }; /* The structure layout is identical to a pair of registers in SET_*_REG_PAIRS_PACKED. */ diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index b90a94ec337..c9c34e9d0b5 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -5030,7 +5030,7 @@ radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer, const struct radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.render.ds_att.ds, iview, false); } - cmd_buffer->cs->context_roll_without_scissor_emitted = true; + cmd_buffer->cs->b->context_roll = true; } /** @@ -5293,7 +5293,7 @@ radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, struct ra assert(cs->b->cdw <= cdw_max); - cmd_buffer->cs->context_roll_without_scissor_emitted = true; + cmd_buffer->cs->b->context_roll = true; } /** @@ -11226,7 +11226,7 @@ radv_get_needed_dynamic_states(struct radv_cmd_buffer *cmd_buffer) static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info *info) { - if (cmd_buffer->cs->context_roll_without_scissor_emitted || info->strmout_va) + if (cmd_buffer->cs->b->context_roll || info->strmout_va) return true; uint64_t used_dynamic_states = radv_get_needed_dynamic_states(cmd_buffer); @@ -12713,7 +12713,7 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r if (late_scissor_emission) { radv_emit_scissor_state(cmd_buffer); - cmd_buffer->cs->context_roll_without_scissor_emitted = false; + cmd_buffer->cs->b->context_roll = false; } } @@ -15345,7 +15345,7 @@ radv_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstC */ radeon_set_context_reg(R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16 * i, sb[i].size >> 2); - cmd_buffer->cs->context_roll_without_scissor_emitted = true; + cmd_buffer->cs->b->context_roll = true; if (append) { radeon_emit(PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0)); @@ -15458,7 +15458,7 @@ radv_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCou radeon_end(); - cmd_buffer->cs->context_roll_without_scissor_emitted = true; + cmd_buffer->cs->b->context_roll = true; } } diff --git a/src/amd/vulkan/radv_cmd_buffer.h b/src/amd/vulkan/radv_cmd_buffer.h index 6a937c6dac2..106af552ecf 100644 --- a/src/amd/vulkan/radv_cmd_buffer.h +++ b/src/amd/vulkan/radv_cmd_buffer.h @@ -467,9 +467,8 @@ struct radv_cmd_buffer_upload { struct radv_cmd_stream { struct ac_cmdbuf *b; - bool context_roll_without_scissor_emitted; - struct ac_tracked_regs tracked_regs; + enum amd_ip_type hw_ip; struct ac_buffered_sh_regs buffered_sh_regs; diff --git a/src/amd/vulkan/radv_cs.c b/src/amd/vulkan/radv_cs.c index ed2e1ff17a2..578d65971b9 100644 --- a/src/amd/vulkan/radv_cs.c +++ b/src/amd/vulkan/radv_cs.c @@ -450,7 +450,6 @@ radv_init_cmd_stream(const struct radv_device *device, struct radv_cmd_stream *c { const struct radv_physical_device *pdev = radv_device_physical(device); - cs->context_roll_without_scissor_emitted = false; cs->buffered_sh_regs.num = 0; cs->hw_ip = ip_type; diff --git a/src/amd/vulkan/radv_cs.h b/src/amd/vulkan/radv_cs.h index 1e323904929..8590e3aa509 100644 --- a/src/amd/vulkan/radv_cs.h +++ b/src/amd/vulkan/radv_cs.h @@ -61,7 +61,7 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need radeon_set_context_reg(reg, __value); \ BITSET_SET(__tracked_regs->reg_saved_mask, (reg_enum)); \ __tracked_regs->reg_value[(reg_enum)] = __value; \ - __rcs->context_roll_without_scissor_emitted = true; \ + __cs->context_roll = true; \ } \ } while (0) @@ -77,7 +77,7 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need BITSET_SET_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 1); \ __tracked_regs->reg_value[(reg_enum)] = __v1; \ __tracked_regs->reg_value[(reg_enum) + 1] = __v2; \ - __rcs->context_roll_without_scissor_emitted = true; \ + __cs->context_roll = true; \ } \ } while (0) @@ -96,7 +96,7 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need __tracked_regs->reg_value[(reg_enum)] = __v1; \ __tracked_regs->reg_value[(reg_enum) + 1] = __v2; \ __tracked_regs->reg_value[(reg_enum) + 2] = __v3; \ - __rcs->context_roll_without_scissor_emitted = true; \ + __cs->context_roll = true; \ } \ } while (0) @@ -117,7 +117,7 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need __tracked_regs->reg_value[(reg_enum) + 1] = __v2; \ __tracked_regs->reg_value[(reg_enum) + 2] = __v3; \ __tracked_regs->reg_value[(reg_enum) + 3] = __v4; \ - __rcs->context_roll_without_scissor_emitted = true; \ + __cs->context_roll = true; \ } \ } while (0) @@ -127,7 +127,7 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need radeon_set_context_reg_seq(reg, num); \ radeon_emit_array(values, num); \ memcpy(saved_values, values, sizeof(uint32_t) * (num)); \ - __rcs->context_roll_without_scissor_emitted = true; \ + __cs->context_roll = true; \ } \ } while (0)