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r600g: add clip_misc_state for clip registers emitted in draw_vbo

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Reviewed-by: Jerome Glisse <jglisse@redhat.com>
This commit is contained in:
Marek Olšák 2012-09-10 21:38:09 +02:00
parent 51d839edc8
commit c56dca909a
8 changed files with 44 additions and 22 deletions
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4
src/gallium/drivers/r600/evergreen_hw_context.c
View file

@ -137,9 +137,7 @@ static const struct r600_reg evergreen_context_reg_list[] = {
{R_028800_DB_DEPTH_CONTROL, 0, 0},
{R_02880C_DB_SHADER_CONTROL, 0, 0},
{R_028808_CB_COLOR_CONTROL, 0, 0},
{R_028810_PA_CL_CLIP_CNTL, 0, 0},
{R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
{R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
{R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
{R_028844_SQ_PGM_RESOURCES_PS, 0, 0},
{R_02884C_SQ_PGM_EXPORTS_PS, 0, 0},
@ -430,9 +428,7 @@ static const struct r600_reg cayman_context_reg_list[] = {
{CM_R_028804_DB_EQAA},
{R_028808_CB_COLOR_CONTROL, 0, 0},
{R_02880C_DB_SHADER_CONTROL, 0, 0},
{R_028810_PA_CL_CLIP_CNTL, 0, 0},
{R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
{R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
{R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0},
{R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
{R_028844_SQ_PGM_RESOURCES_PS, 0, 0},

1
src/gallium/drivers/r600/evergreen_state.c
View file

@ -2160,6 +2160,7 @@ void evergreen_init_state_functions(struct r600_context *rctx)
r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 7);
r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);

3
src/gallium/drivers/r600/r600_hw_context.c
View file

@ -357,9 +357,7 @@ static const struct r600_reg r600_context_reg_list[] = {
{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
{R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
{R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
{R_028810_PA_CL_CLIP_CNTL, 0, 0},
{R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
{R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
{R_028A00_PA_SU_POINT_SIZE, 0, 0},
{R_028A04_PA_SU_POINT_MINMAX, 0, 0},
{R_028A08_PA_SU_LINE_CNTL, 0, 0},
@ -1019,6 +1017,7 @@ void r600_begin_new_cs(struct r600_context *ctx)
r600_atom_dirty(ctx, &ctx->alphatest_state.atom);
r600_atom_dirty(ctx, &ctx->blend_color.atom);
r600_atom_dirty(ctx, &ctx->cb_misc_state.atom);
r600_atom_dirty(ctx, &ctx->clip_misc_state.atom);
r600_atom_dirty(ctx, &ctx->clip_state.atom);
r600_atom_dirty(ctx, &ctx->db_misc_state.atom);
r600_atom_dirty(ctx, &ctx->sample_mask.atom);

13
src/gallium/drivers/r600/r600_pipe.h
View file

@ -35,7 +35,7 @@
#include "r600_resource.h"
#include "evergreen_compute.h"
#define R600_NUM_ATOMS 24
#define R600_NUM_ATOMS 25
#define R600_MAX_CONST_BUFFERS 2
#define R600_MAX_CONST_BUFFER_SIZE 4096
@ -84,6 +84,14 @@ struct r600_cb_misc_state {
bool dual_src_blend;
};
struct r600_clip_misc_state {
struct r600_atom atom;
unsigned pa_cl_clip_cntl; /* from rasterizer */
unsigned pa_cl_vs_out_cntl; /* from vertex shader */
unsigned clip_plane_enable; /* from rasterizer */
unsigned clip_dist_write; /* from vertex shader */
};
struct r600_alphatest_state {
struct r600_atom atom;
unsigned sx_alpha_test_control; /* this comes from dsa state */
@ -344,7 +352,6 @@ struct r600_context {
unsigned compute_cb_target_mask;
unsigned db_shader_control;
unsigned pa_sc_line_stipple;
unsigned pa_cl_clip_cntl;
/* for saving when using blitter */
struct r600_pipe_shader_selector *ps_shader;
struct r600_pipe_shader_selector *vs_shader;
@ -383,6 +390,7 @@ struct r600_context {
struct r600_alphatest_state alphatest_state;
struct r600_blend_color blend_color;
struct r600_cb_misc_state cb_misc_state;
struct r600_clip_misc_state clip_misc_state;
struct r600_clip_state clip_state;
struct r600_db_misc_state db_misc_state;
struct r600_seamless_cube_map seamless_cube_map;
@ -590,6 +598,7 @@ void r600_translate_index_buffer(struct r600_context *r600,
void r600_init_common_state_functions(struct r600_context *rctx);
void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom);
void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,

3
src/gallium/drivers/r600/r600_shader.c
View file

@ -1324,8 +1324,7 @@ static int r600_shader_from_tgsi(struct r600_context * rctx, struct r600_pipe_sh
shader->fs_write_all = TRUE;
break;
case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
if (property->u[0].Data == 1)
shader->vs_prohibit_ucps = TRUE;
/* we don't need this one */
break;
}
break;

1
src/gallium/drivers/r600/r600_shader.h
View file

@ -47,7 +47,6 @@ struct r600_shader {
struct r600_shader_io output[32];
boolean uses_kill;
boolean fs_write_all;
boolean vs_prohibit_ucps;
boolean two_side;
/* Number of color outputs in the TGSI shader,
* sometimes it could be higher than nr_cbufs (bug?).

1
src/gallium/drivers/r600/r600_state.c
View file

@ -2041,6 +2041,7 @@ void r600_init_state_functions(struct r600_context *rctx)
r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 4);
r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);

40
src/gallium/drivers/r600/r600_state_common.c
View file

@ -312,7 +312,6 @@ static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
rctx->sprite_coord_enable = rs->sprite_coord_enable;
rctx->two_side = rs->two_side;
rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
rctx->multisample_enable = rs->multisample_enable;
rctx->rasterizer = rs;
@ -326,6 +325,14 @@ static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
r600_polygon_offset_update(rctx);
}
/* Update clip_misc_state. */
if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
r600_atom_dirty(rctx, &rctx->clip_misc_state.atom);
}
/* Workaround for a missing scissor enable on r600. */
if (rctx->chip_class == R600) {
if (rs->scissor_enable != rctx->scissor_enable) {
@ -873,6 +880,14 @@ static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
if (rctx->chip_class < EVERGREEN && rctx->ps_shader)
r600_adjust_gprs(rctx);
/* Update clip misc state. */
if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write) {
rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
r600_atom_dirty(rctx, &rctx->clip_misc_state.atom);
}
}
}
@ -1133,6 +1148,19 @@ static unsigned r600_conv_prim_to_gs_out(unsigned mode)
return prim_conv[mode];
}
void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
{
struct radeon_winsys_cs *cs = rctx->cs;
struct r600_clip_misc_state *state = &rctx->clip_misc_state;
r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
state->pa_cl_clip_cntl |
(state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F));
r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
state->pa_cl_vs_out_cntl |
(state->clip_plane_enable & state->clip_dist_write));
}
static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
{
struct r600_context *rctx = (struct r600_context *)ctx;
@ -1186,8 +1214,6 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart);
r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0);
}
rctx->vgt.nregs = 0;
@ -1204,14 +1230,6 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
prim == V_008958_DI_PT_LINELOOP)
ls_mask = 2;
r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
r600_pipe_state_mod_reg(&rctx->vgt,
rctx->vs_shader->current->pa_cl_vs_out_cntl |
(rctx->rasterizer->clip_plane_enable & rctx->vs_shader->current->shader.clip_dist_write));
r600_pipe_state_mod_reg(&rctx->vgt,
rctx->pa_cl_clip_cntl |
(rctx->vs_shader->current->shader.clip_dist_write ||
rctx->vs_shader->current->shader.vs_prohibit_ucps ?
0 : rctx->rasterizer->clip_plane_enable & 0x3F));
r600_context_pipe_state_set(rctx, &rctx->vgt);