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i965: Add support for GL_ARB_cull_distance

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Signed-off-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Kristian Høgsberg Kristensen 2016-05-12 17:38:56 -07:00
parent a1c2444792
commit c564348a2e
9 changed files with 23 additions and 3 deletions
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2
src/mesa/drivers/dri/i965/brw_compiler.h
View file

@ -592,6 +592,8 @@ struct brw_vue_prog_data {
GLuint urb_read_length;
GLuint total_grf;
uint32_t cull_distance_mask;
/* Used for calculating urb partitions. In the VS, this is the size of the
* URB entry used for both input and output to the thread. In the GS, this
* is the size of the URB entry used for output.

4
src/mesa/drivers/dri/i965/brw_gs.c
View file

@ -138,6 +138,10 @@ brw_codegen_gs_prog(struct brw_context *brw,
GLbitfield64 outputs_written = gp->program.Base.OutputsWritten;
prog_data.base.cull_distance_mask =
((1 << gp->program.Base.CullDistanceArraySize) - 1) <<
gp->program.Base.ClipDistanceArraySize;
brw_compute_vue_map(brw->intelScreen->devinfo,
&prog_data.base.vue_map, outputs_written,
prog ? prog->SeparateShader : false);

4
src/mesa/drivers/dri/i965/brw_tes.c
View file

@ -164,6 +164,10 @@ brw_codegen_tes_prog(struct brw_context *brw,
prog_data.base.base.nr_params = param_count;
prog_data.base.base.nr_image_params = tes->NumImages;
prog_data.base.cull_distance_mask =
((1 << tep->program.Base.CullDistanceArraySize) - 1) <<
tep->program.Base.ClipDistanceArraySize;
brw_nir_setup_glsl_uniforms(nir, shader_prog, &tep->program.Base,
&prog_data.base.base,
compiler->scalar_stage[MESA_SHADER_TESS_EVAL]);

4
src/mesa/drivers/dri/i965/brw_vs.c
View file

@ -118,6 +118,10 @@ brw_codegen_vs_prog(struct brw_context *brw,
prog_data.inputs_read |= VERT_BIT_EDGEFLAG;
}
prog_data.base.cull_distance_mask =
((1 << vp->program.Base.CullDistanceArraySize) - 1) <<
vp->program.Base.ClipDistanceArraySize;
if (brw->gen < 6) {
/* Put dummy slots into the VUE for the SF to put the replaced
* point sprite coords in. We shouldn't need these dummy slots,

2
src/mesa/drivers/dri/i965/gen6_clip_state.c
View file

@ -50,6 +50,8 @@ upload_clip_state(struct brw_context *brw)
dw2 |= GEN6_CLIP_NON_PERSPECTIVE_BARYCENTRIC_ENABLE;
}
dw1 |= brw->vs.prog_data->base.cull_distance_mask;
if (brw->gen >= 7)
dw1 |= GEN7_CLIP_EARLY_CULL;

3
src/mesa/drivers/dri/i965/gen8_ds_state.c
View file

@ -69,7 +69,8 @@ gen8_upload_ds_state(struct brw_context *brw)
GEN7_DS_SIMD8_DISPATCH_ENABLE : 0) |
(tes_prog_data->domain == BRW_TESS_DOMAIN_TRI ?
GEN7_DS_COMPUTE_W_COORDINATE_ENABLE : 0));
OUT_BATCH(SET_FIELD(ctx->Transform.ClipPlanesEnabled,
OUT_BATCH(SET_FIELD(vue_prog_data->cull_distance_mask |
ctx->Transform.ClipPlanesEnabled,
GEN8_DS_USER_CLIP_DISTANCE));
if (brw->gen >= 9) {

3
src/mesa/drivers/dri/i965/gen8_gs_state.c
View file

@ -108,7 +108,8 @@ gen8_upload_gs_state(struct brw_context *brw)
OUT_BATCH(dw8);
/* DW9 / _NEW_TRANSFORM */
OUT_BATCH((ctx->Transform.ClipPlanesEnabled <<
OUT_BATCH((prog_data->cull_distance_mask |
ctx->Transform.ClipPlanesEnabled <<
GEN8_GS_USER_CLIP_DISTANCE_SHIFT) |
(urb_entry_output_length << GEN8_GS_URB_OUTPUT_LENGTH_SHIFT) |
(urb_entry_write_offset <<

3
src/mesa/drivers/dri/i965/gen8_vs_state.c
View file

@ -77,7 +77,8 @@ upload_vs_state(struct brw_context *brw)
GEN6_VS_ENABLE);
/* _NEW_TRANSFORM */
OUT_BATCH((ctx->Transform.ClipPlanesEnabled <<
OUT_BATCH(prog_data->cull_distance_mask |
(ctx->Transform.ClipPlanesEnabled <<
GEN8_VS_USER_CLIP_DISTANCE_SHIFT));
ADVANCE_BATCH();
}

1
src/mesa/drivers/dri/i965/intel_extensions.c
View file

@ -289,6 +289,7 @@ intelInitExtensions(struct gl_context *ctx)
ctx->Extensions.ARB_blend_func_extended =
!driQueryOptionb(&brw->optionCache, "disable_blend_func_extended");
ctx->Extensions.ARB_conditional_render_inverted = true;
ctx->Extensions.ARB_cull_distance = true;
ctx->Extensions.ARB_draw_buffers_blend = true;
ctx->Extensions.ARB_ES3_compatibility = true;
ctx->Extensions.ARB_fragment_layer_viewport = true;