From c53641f810de39d6ce0cd7865784a5e2b2ce53bd Mon Sep 17 00:00:00 2001 From: David Rosca Date: Sat, 24 Aug 2024 09:39:17 +0200 Subject: [PATCH] radeonsi: Implement buf_ofst_info in si_video_resize_buffer GPU copy path This is used when resizing VP9 Tier1 DPB. Fixes: 322240fcff1 ("radeonsi: Add GPU copy path to si_video_resize_buffer") Reviewed-by: Boyuan Zhang Reviewed-by: Ruijing Dong Part-of: --- src/gallium/drivers/radeonsi/radeon_video.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/radeonsi/radeon_video.c b/src/gallium/drivers/radeonsi/radeon_video.c index 3cb37d1eb29..95bc03bc60a 100644 --- a/src/gallium/drivers/radeonsi/radeon_video.c +++ b/src/gallium/drivers/radeonsi/radeon_video.c @@ -108,9 +108,20 @@ bool si_vid_resize_buffer(struct pipe_context *context, struct radeon_cmdbuf *cs ws->buffer_unmap(ws, new_buf->res->buf); ws->buffer_unmap(ws, old_buf.res->buf); } else { - bytes = MIN2(new_buf->res->b.b.width0, old_buf.res->b.b.width0); - si_copy_buffer(sctx, &new_buf->res->b.b, &old_buf.res->b.b, - 0, 0, bytes, SI_OP_SYNC_BEFORE); + if (buf_ofst_info) { + uint64_t dst_offset = 0, src_offset = 0; + for (int i = 0; i < buf_ofst_info->num_units; i++) { + si_copy_buffer(sctx, &new_buf->res->b.b, &old_buf.res->b.b, + dst_offset, src_offset, buf_ofst_info->old_offset, + i == 0 ? SI_OP_SYNC_BEFORE : 0); + dst_offset += buf_ofst_info->new_offset; + src_offset += buf_ofst_info->old_offset; + } + } else { + bytes = MIN2(new_buf->res->b.b.width0, old_buf.res->b.b.width0); + si_copy_buffer(sctx, &new_buf->res->b.b, &old_buf.res->b.b, + 0, 0, bytes, SI_OP_SYNC_BEFORE); + } context->flush(context, NULL, 0); }