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freedreno/a6xx: Support GL_ARB_viewport_array + gl43
Support multiple viewports and bump supported GLSL version now that we tick all the boxes. Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>
This commit is contained in:
Rob Clark
Marge Bot
parent
23b7948a72
commit
c50e9f65bd
12 changed files with 119 additions and 61 deletions
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@ -145,9 +145,9 @@ GL 4.1, GLSL 4.10 --- all DONE: i965/gen7+, nvc0, r600, radeonsi, llvmpipe, virg
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GL_ARB_ES2_compatibility DONE (freedreno, i965, nv50, softpipe, v3d, vc4, panfrost, lima)
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GL_ARB_get_program_binary DONE (freedreno, v3d, 0 or 1 binary formats)
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GL_ARB_separate_shader_objects DONE (all drivers)
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GL_ARB_shader_precision DONE (i965/gen7+, all drivers that support GLSL 4.10)
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GL_ARB_vertex_attrib_64bit DONE (i965/gen7+, softpipe, )
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GL_ARB_viewport_array DONE (i965, nv50, softpipe, )
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GL_ARB_shader_precision DONE (freedreno/a6xx, i965/gen7+, all drivers that support GLSL 4.10)
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GL_ARB_vertex_attrib_64bit DONE (freedreno/a6xx, i965/gen7+, softpipe, )
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GL_ARB_viewport_array DONE (freedreno/a6xx, i965, nv50, softpipe, )
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GL 4.2, GLSL 4.20 -- all DONE: i965/gen7+, nvc0, r600, radeonsi, llvmpipe, virgl, zink, d3d12
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@ -175,7 +175,7 @@ GL 4.3, GLSL 4.30 -- all DONE: i965/gen8+, nvc0, r600, radeonsi, llvmpipe, virgl
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GL_ARB_copy_image DONE (freedreno/a6xx, i965, nv50, softpipe, v3d)
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GL_KHR_debug DONE (all drivers)
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GL_ARB_explicit_uniform_location DONE (all drivers that support GLSL)
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GL_ARB_fragment_layer_viewport DONE (i965, nv50, softpipe, d3d12)
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GL_ARB_fragment_layer_viewport DONE (freedreno/a6xx, i965, nv50, softpipe, d3d12)
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GL_ARB_framebuffer_no_attachments DONE (freedreno, i965, softpipe, v3d, d3d12)
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GL_ARB_internalformat_query2 DONE (all drivers)
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GL_ARB_invalidate_subdata DONE (all drivers)
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@ -346,7 +346,7 @@ Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES ve
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GL_OES_texture_half_float DONE (freedreno, i965, r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe, panfrost, v3d, zink, lima)
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GL_OES_texture_half_float_linear DONE (freedreno, i965, r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe, panfrost, v3d, zink, lima)
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GL_OES_texture_view DONE (freedreno, i965/gen8+, r600, radeonsi, nv50, nvc0, softpipe, llvmpipe, v3d, zink)
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GL_OES_viewport_array DONE (i965, nvc0, r600, radeonsi, softpipe, zink)
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GL_OES_viewport_array DONE (freedreno/a6xx, i965, nvc0, r600, radeonsi, softpipe, zink)
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GLX_ARB_context_flush_control DONE (all drivers)
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GLX_ARB_robustness_application_isolation not started
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GLX_ARB_robustness_share_group_isolation not started
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@ -40,7 +40,7 @@ caselists = [
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"/deqp/mustpass/gles2-khr-master.txt",
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"/deqp/mustpass/gles3-khr-master.txt",
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"/deqp/mustpass/gles31-khr-master.txt",
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"/deqp/mustpass/gl33-master.txt",
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"/deqp/mustpass/gl43-master.txt",
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]
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skips = ["install/freedreno-a630-premerge-skips.txt"]
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deqp_args = [
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@ -3,7 +3,7 @@
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# delete lines from the test list. Be careful.
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# Timeouts, passes otherwise
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KHR-GL33.texture_swizzle.smoke
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KHR-GL43.texture_swizzle.smoke
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# These generally take near 15 seconds. The time is spent inside dEQP.
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dEQP-VK.tessellation.invariance.inner_triangle_set.quads_equal_spacing
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@ -1,8 +1,21 @@
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# Test bug, using GLSL 4.20 on a 3.3 context.
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# Broken in VK-GL-CTS e5c45899ed7e90fb616ccd1d3c66e6eded120684
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KHR-GL33.cull_distance.coverage,Fail
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# Shader compilation error log: 0:6(1): error: invalid stream specified 1 is larger than MAX_VERTEX_STREAMS - 1
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KHR-GL43.transform_feedback.draw_xfb_stream_instanced_test,Fail
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KHR-GL33.transform_feedback.draw_xfb_stream_instanced_test,Fail
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# glGetError() returned GL_INVALID_ENUM at gl4cMapBufferAlignmentTests.cpp:279
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KHR-GL43.map_buffer_alignment.functional,Fail
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KHR-GL43.gpu_shader_fp64.fp64.max_uniform_components,Fail
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KHR-GL43.gpu_shader_fp64.builtin.mod_dvec2,Fail
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KHR-GL43.gpu_shader_fp64.builtin.mod_dvec3,Fail
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KHR-GL43.gpu_shader_fp64.builtin.mod_dvec4,Fail
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KHR-GL43.shader_subroutine.control_flow_and_returned_subroutine_values_used_as_subroutine_input,Fail
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KHR-GL43.shader_image_load_store.basic-allFormats-store,Fail
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KHR-GL43.shader_image_load_store.basic-allTargets-store,Fail
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KHR-GL43.shader_image_load_store.non-layered_binding,Fail
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KHR-GL43.shading_language_420pack.binding_images,Fail
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KHR-GL43.copy_image.functional,Fail
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KHR-GL43.compute_shader.conditional-dispatching,Fail
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KHR-GL43.vertex_attrib_binding.advanced-largeStrideAndOffsetsNewAndLegacyAPI,Fail
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# Lots of errors like "[279] Check failed. Received: [3,0,0,2] instead of: [5,0,0,2]"
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KHR-GLES31.core.geometry_shader.layered_framebuffer.depth_support,Fail
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@ -16,6 +29,9 @@ KHR-GLES31.core.tessellation_shader.tessellation_shader_tc_barriers.barrier_guar
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# https://gitlab.freedesktop.org/mesa/mesa/-/issues/5582
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KHR-GLES31.core.texture_cube_map_array.color_depth_attachments,Fail
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# glsl parser bug will go away when we expose gl44 and/or GL_ARB_enhanced_layouts
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KHR-GL33.CommonBugs.CommonBug_ParenthesisInLayoutQualifierIntegerValue,Fail
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# rendering errors in ~4x4 blocks around the bottom side of the diagonal for the quad
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bypass-dEQP-GLES31.functional.blend_equation_advanced.msaa.colorburn,Fail
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bypass-dEQP-GLES31.functional.blend_equation_advanced.msaa.colordodge,Fail
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@ -354,7 +370,6 @@ spec@!opengl 1.0@depth-clear-precision-check,Fail
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spec@!opengl 1.0@depth-clear-precision-check@depth24,Fail
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spec@!opengl 1.0@depth-clear-precision-check@depth24_stencil8,Fail
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spec@!opengl 1.0@depth-clear-precision-check@depth32,Fail
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spec@arb_texture_buffer_object@texture-buffer-size-clamp,Fail
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# https://gitlab.khronos.org/Tracker/vk-gl-cts/-/issues/3759
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# deqp-vk: ../src/freedreno/vulkan/tu_pipeline.c:3894: tu_pipeline_builder_init_graphics: Assertion `subpass->color_count == 0 || !create_info->pColorBlendState || subpass->color_count == create_info->pColorBlendState->attachmentCount' failed
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@ -89,7 +89,10 @@ dEQP-GLES3.functional.fbo.blit.conversion.rg8i_to_r16i
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dEQP-GLES3.functional.fbo.blit.conversion.rg8_to_r16f
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# First noticed Jun 1 2020 on an innocent branch.
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KHR-GL33.packed_depth_stencil.verify_copy_tex_image.depth32f_stencil8
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KHR-GL43.packed_depth_stencil.verify_copy_tex_image.depth32f_stencil8
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KHR-GL43.shader_image_size.basic-nonMS-fs-float
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KHR-GL43.shader_image_size.advanced-nonMS-fs-float
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# Flaky with introduction of testing
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KHR-GLES31.core.arrays_of_arrays.InteractionFunctionCalls2
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@ -3,4 +3,6 @@
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# delete lines from the test list. Be careful.
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# Timeouts, passes otherwise
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KHR-GL33.texture_swizzle.smoke
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KHR-GL43.texture_swizzle.smoke
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KHR-GL43.gpu_shader_fp64.builtin.inverse_dmat4
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KHR-GL43.gpu_shader_fp64.fp64.varyings
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@ -36,6 +36,7 @@ KHR-GLES31.core.shader_image_load_store.basic-allFormats-store-fs
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# 60s timeout
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KHR-GLES31.core.tessellation_shader.tessellation_control_to_tessellation_evaluation.gl_MaxPatchVertices_Position_PointSize
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KHR-GL43.copy_image.functional
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# These take most of a minute to run
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spec@!opengl 3.0@clearbuffer-depth-cs-probe
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@ -187,7 +187,8 @@ setup_state_map(struct fd_context *ctx)
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/* NOTE: scissor enabled bit is part of rasterizer state, but
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* fd_rasterizer_state_bind() will mark scissor dirty if needed:
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*/
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fd_context_add_map(ctx, FD_DIRTY_SCISSOR, BIT(FD6_GROUP_SCISSOR));
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fd_context_add_map(ctx, FD_DIRTY_SCISSOR | FD_DIRTY_PROG,
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BIT(FD6_GROUP_SCISSOR));
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/* Stuff still emit in IB2
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*
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@ -195,7 +196,7 @@ setup_state_map(struct fd_context *ctx)
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* move it into FD6_GROUP_RASTERIZER?
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*/
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fd_context_add_map(
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ctx, FD_DIRTY_STENCIL_REF | FD_DIRTY_VIEWPORT | FD_DIRTY_RASTERIZER,
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ctx, FD_DIRTY_STENCIL_REF | FD_DIRTY_VIEWPORT | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG,
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BIT(FD6_GROUP_NON_GROUP));
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}
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@ -730,15 +730,19 @@ static struct fd_ringbuffer *
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build_scissor(struct fd6_emit *emit) assert_dt
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{
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struct fd_context *ctx = emit->ctx;
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struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
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struct pipe_scissor_state *scissors = fd_context_get_scissor(ctx);
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unsigned num_viewports = emit->prog->num_viewports;
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struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
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emit->ctx->batch->submit, 3 * 4, FD_RINGBUFFER_STREAMING);
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emit->ctx->batch->submit, (1 + (2 * num_viewports)) * 4, FD_RINGBUFFER_STREAMING);
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OUT_REG(
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ring,
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A6XX_GRAS_SC_SCREEN_SCISSOR_TL(0, .x = scissor->minx, .y = scissor->miny),
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A6XX_GRAS_SC_SCREEN_SCISSOR_BR(0, .x = scissor->maxx, .y = scissor->maxy));
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OUT_PKT4(ring, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(0), 2 * num_viewports);
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for (unsigned i = 0; i < num_viewports; i++) {
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OUT_RING(ring, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(scissors[i].minx) |
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A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(scissors[i].miny));
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OUT_RING(ring, A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(scissors[i].maxx) |
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A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(scissors[i].maxy));
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}
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return ring;
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}
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@ -954,6 +958,7 @@ fd6_emit_non_ring(struct fd_ringbuffer *ring, struct fd6_emit *emit) assert_dt
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{
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struct fd_context *ctx = emit->ctx;
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const enum fd_dirty_3d_state dirty = emit->dirty;
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unsigned num_viewports = emit->prog->num_viewports;
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if (dirty & FD_DIRTY_STENCIL_REF) {
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struct pipe_stencil_ref *sr = &ctx->stencil_ref;
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@ -963,23 +968,27 @@ fd6_emit_non_ring(struct fd_ringbuffer *ring, struct fd6_emit *emit) assert_dt
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A6XX_RB_STENCILREF_BFREF(sr->ref_value[1]));
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}
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if (dirty & FD_DIRTY_VIEWPORT) {
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struct pipe_scissor_state *scissor = &ctx->viewport_scissor[0];
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struct pipe_viewport_state *vp = & ctx->viewport[0];
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if (dirty & (FD_DIRTY_VIEWPORT | FD_DIRTY_PROG)) {
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for (unsigned i = 0; i < num_viewports; i++) {
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struct pipe_scissor_state *scissor = &ctx->viewport_scissor[i];
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struct pipe_viewport_state *vp = & ctx->viewport[i];
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OUT_REG(ring, A6XX_GRAS_CL_VPORT_XOFFSET(0, vp->translate[0]),
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A6XX_GRAS_CL_VPORT_XSCALE(0, vp->scale[0]),
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A6XX_GRAS_CL_VPORT_YOFFSET(0, vp->translate[1]),
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A6XX_GRAS_CL_VPORT_YSCALE(0, vp->scale[1]),
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A6XX_GRAS_CL_VPORT_ZOFFSET(0, vp->translate[2]),
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A6XX_GRAS_CL_VPORT_ZSCALE(0, vp->scale[2]));
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OUT_REG(ring, A6XX_GRAS_CL_VPORT_XOFFSET(i, vp->translate[0]),
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A6XX_GRAS_CL_VPORT_XSCALE(i, vp->scale[0]),
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A6XX_GRAS_CL_VPORT_YOFFSET(i, vp->translate[1]),
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A6XX_GRAS_CL_VPORT_YSCALE(i, vp->scale[1]),
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A6XX_GRAS_CL_VPORT_ZOFFSET(i, vp->translate[2]),
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A6XX_GRAS_CL_VPORT_ZSCALE(i, vp->scale[2]));
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OUT_REG(
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ring,
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A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(0, .x = scissor->minx,
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.y = scissor->miny),
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A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(0, .x = scissor->maxx,
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.y = scissor->maxy));
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OUT_REG(
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ring,
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A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(i,
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.x = scissor->minx,
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.y = scissor->miny),
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A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(i,
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.x = scissor->maxx,
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.y = scissor->maxy));
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}
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OUT_REG(ring, A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ(.horz = ctx->guardband.x,
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.vert = ctx->guardband.y));
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@ -988,18 +997,22 @@ fd6_emit_non_ring(struct fd_ringbuffer *ring, struct fd6_emit *emit) assert_dt
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/* The clamp ranges are only used when the rasterizer wants depth
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* clamping.
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*/
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if ((dirty & (FD_DIRTY_VIEWPORT | FD_DIRTY_RASTERIZER)) &&
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if ((dirty & (FD_DIRTY_VIEWPORT | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) &&
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fd_depth_clamp_enabled(ctx)) {
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struct pipe_viewport_state *vp = & ctx->viewport[0];
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float zmin, zmax;
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for (unsigned i = 0; i < num_viewports; i++) {
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struct pipe_viewport_state *vp = & ctx->viewport[i];
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float zmin, zmax;
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util_viewport_zmin_zmax(vp, ctx->rasterizer->clip_halfz,
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&zmin, &zmax);
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util_viewport_zmin_zmax(vp, ctx->rasterizer->clip_halfz,
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&zmin, &zmax);
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OUT_REG(ring, A6XX_GRAS_CL_Z_CLAMP_MIN(0, zmin),
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A6XX_GRAS_CL_Z_CLAMP_MAX(0, zmax));
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OUT_REG(ring, A6XX_GRAS_CL_Z_CLAMP_MIN(i, zmin),
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A6XX_GRAS_CL_Z_CLAMP_MAX(i, zmax));
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OUT_REG(ring, A6XX_RB_Z_CLAMP_MIN(zmin), A6XX_RB_Z_CLAMP_MAX(zmax));
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/* TODO: what to do about this and multi viewport ? */
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if (i == 0)
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OUT_REG(ring, A6XX_RB_Z_CLAMP_MIN(zmin), A6XX_RB_Z_CLAMP_MAX(zmax));
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}
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}
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}
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@ -400,14 +400,14 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
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uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
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uint32_t smask_in_regid, smask_regid;
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uint32_t stencilref_regid;
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uint32_t vertex_regid, instance_regid, layer_regid, vs_primitive_regid;
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uint32_t vertex_regid, instance_regid, layer_regid, view_regid, vs_primitive_regid;
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uint32_t hs_invocation_regid;
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uint32_t tess_coord_x_regid, tess_coord_y_regid, hs_rel_patch_regid,
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ds_rel_patch_regid, ds_primitive_regid;
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uint32_t ij_regid[IJ_COUNT];
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uint32_t gs_header_regid;
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enum a6xx_threadsize fssz;
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uint8_t psize_loc = ~0, pos_loc = ~0, layer_loc = ~0;
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uint8_t psize_loc = ~0, pos_loc = ~0, layer_loc = ~0, view_loc =~0;
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uint8_t clip0_loc, clip1_loc;
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int i, j;
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@ -417,6 +417,8 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
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const struct ir3_shader_variant *ds = state->ds;
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const struct ir3_shader_variant *gs = state->gs;
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const struct ir3_shader_variant *fs = binning_pass ? &dummy_fs : state->fs;
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const struct ir3_shader_variant *last_shader = binning_pass ? state->bs :
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fd6_last_shader(state);
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/* binning VS is wrong when GS is present, so use nonbinning VS
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* TODO: compile both binning VS/GS variants correctly
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@ -428,11 +430,12 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
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fssz = fs->info.double_threadsize ? THREAD128 : THREAD64;
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pos_regid = ir3_find_output_regid(vs, VARYING_SLOT_POS);
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psize_regid = ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
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clip0_regid = ir3_find_output_regid(vs, VARYING_SLOT_CLIP_DIST0);
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clip1_regid = ir3_find_output_regid(vs, VARYING_SLOT_CLIP_DIST1);
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layer_regid = ir3_find_output_regid(vs, VARYING_SLOT_LAYER);
|
||||
pos_regid = ir3_find_output_regid(last_shader, VARYING_SLOT_POS);
|
||||
psize_regid = ir3_find_output_regid(last_shader, VARYING_SLOT_PSIZ);
|
||||
clip0_regid = ir3_find_output_regid(last_shader, VARYING_SLOT_CLIP_DIST0);
|
||||
clip1_regid = ir3_find_output_regid(last_shader, VARYING_SLOT_CLIP_DIST1);
|
||||
layer_regid = ir3_find_output_regid(last_shader, VARYING_SLOT_LAYER);
|
||||
view_regid = ir3_find_output_regid(last_shader, VARYING_SLOT_VIEWPORT);
|
||||
vertex_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
|
||||
instance_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
|
||||
if (hs)
|
||||
|
|
@ -475,7 +478,6 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
|
|||
psize_regid = ir3_find_output_regid(gs, VARYING_SLOT_PSIZ);
|
||||
clip0_regid = ir3_find_output_regid(gs, VARYING_SLOT_CLIP_DIST0);
|
||||
clip1_regid = ir3_find_output_regid(gs, VARYING_SLOT_CLIP_DIST1);
|
||||
layer_regid = ir3_find_output_regid(gs, VARYING_SLOT_LAYER);
|
||||
} else {
|
||||
gs_header_regid = regid(63, 0);
|
||||
}
|
||||
|
|
@ -522,6 +524,9 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
|
|||
if (!key->msaa)
|
||||
smask_regid = regid(63, 0);
|
||||
|
||||
if (!binning_pass)
|
||||
state->num_viewports = VALIDREG(view_regid) ? PIPE_MAX_VIEWPORTS : 1;
|
||||
|
||||
/* we could probably divide this up into things that need to be
|
||||
* emitted if frag-prog is dirty vs if vert-prog is dirty..
|
||||
*/
|
||||
|
|
@ -575,7 +580,6 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
|
|||
}
|
||||
|
||||
struct ir3_shader_linkage l = {0};
|
||||
const struct ir3_shader_variant *last_shader = fd6_last_shader(state);
|
||||
|
||||
bool do_streamout = (last_shader->stream_output.num_outputs > 0);
|
||||
uint8_t clip_mask = last_shader->clip_mask,
|
||||
|
|
@ -611,6 +615,11 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
|
|||
ir3_link_add(&l, VARYING_SLOT_LAYER, layer_regid, 0x1, l.max_loc);
|
||||
}
|
||||
|
||||
if (VALIDREG(view_regid)) {
|
||||
view_loc = l.max_loc;
|
||||
ir3_link_add(&l, VARYING_SLOT_VIEWPORT, view_regid, 0x1, l.max_loc);
|
||||
}
|
||||
|
||||
if (VALIDREG(pos_regid)) {
|
||||
pos_loc = l.max_loc;
|
||||
ir3_link_add(&l, VARYING_SLOT_POS, pos_regid, 0xf, l.max_loc);
|
||||
|
|
@ -830,6 +839,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
|
|||
OUT_RING(ring, A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(l.max_loc) |
|
||||
CONDREG(psize_regid, A6XX_PC_VS_OUT_CNTL_PSIZE) |
|
||||
CONDREG(layer_regid, A6XX_PC_VS_OUT_CNTL_LAYER) |
|
||||
CONDREG(view_regid, A6XX_PC_VS_OUT_CNTL_VIEW) |
|
||||
A6XX_PC_VS_OUT_CNTL_CLIP_MASK(clip_cull_mask));
|
||||
|
||||
OUT_PKT4(ring, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
|
||||
|
|
@ -871,7 +881,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
|
|||
|
||||
OUT_PKT4(ring, REG_A6XX_VPC_VS_LAYER_CNTL, 1);
|
||||
OUT_RING(ring, A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(layer_loc) |
|
||||
A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(0xff));
|
||||
A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(view_loc));
|
||||
|
||||
bool need_size = fs->frag_face || fs->fragcoord_compmask != 0;
|
||||
bool need_size_persamp = false;
|
||||
|
|
@ -979,11 +989,13 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
|
|||
A6XX_VPC_GS_PACK_STRIDE_IN_VPC(l.max_loc));
|
||||
|
||||
OUT_PKT4(ring, REG_A6XX_VPC_GS_LAYER_CNTL, 1);
|
||||
OUT_RING(ring, A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(layer_loc) | 0xff00);
|
||||
OUT_RING(ring, A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(layer_loc) |
|
||||
A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(view_loc));
|
||||
|
||||
OUT_PKT4(ring, REG_A6XX_GRAS_GS_LAYER_CNTL, 1);
|
||||
OUT_RING(ring,
|
||||
CONDREG(layer_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER));
|
||||
CONDREG(layer_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER) |
|
||||
CONDREG(view_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW));
|
||||
|
||||
uint32_t flags_regid =
|
||||
ir3_find_output_regid(gs, VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
|
||||
|
|
@ -1000,6 +1012,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
|
|||
A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(l.max_loc) |
|
||||
CONDREG(psize_regid, A6XX_PC_GS_OUT_CNTL_PSIZE) |
|
||||
CONDREG(layer_regid, A6XX_PC_GS_OUT_CNTL_LAYER) |
|
||||
CONDREG(view_regid, A6XX_PC_GS_OUT_CNTL_VIEW) |
|
||||
COND(gs_reads_primid, A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID) |
|
||||
A6XX_PC_GS_OUT_CNTL_CLIP_MASK(clip_cull_mask));
|
||||
|
||||
|
|
@ -1062,7 +1075,8 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
|
|||
|
||||
OUT_PKT4(ring, REG_A6XX_GRAS_VS_LAYER_CNTL, 1);
|
||||
OUT_RING(ring,
|
||||
CONDREG(layer_regid, A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER));
|
||||
CONDREG(layer_regid, A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER) |
|
||||
CONDREG(view_regid, A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW));
|
||||
}
|
||||
|
||||
OUT_PKT4(ring, REG_A6XX_VPC_VS_CLIP_CNTL, 1);
|
||||
|
|
@ -1215,7 +1229,8 @@ emit_interp_state(struct fd_ringbuffer *ring, const struct fd6_program_state *st
|
|||
vinterp[loc / 16] |= INTERP_ONE << ((loc % 16) * 2);
|
||||
loc++;
|
||||
}
|
||||
} else if (fs->inputs[j].slot == VARYING_SLOT_LAYER) {
|
||||
} else if (fs->inputs[j].slot == VARYING_SLOT_LAYER ||
|
||||
fs->inputs[j].slot == VARYING_SLOT_VIEWPORT) {
|
||||
const struct ir3_shader_variant *last_shader = fd6_last_shader(state);
|
||||
uint32_t loc = inloc;
|
||||
|
||||
|
|
@ -1223,7 +1238,7 @@ emit_interp_state(struct fd_ringbuffer *ring, const struct fd6_program_state *st
|
|||
* implicitly zero and the FS is supposed to read zero.
|
||||
*/
|
||||
if (ir3_find_output(last_shader, fs->inputs[j].slot) < 0 &&
|
||||
(compmask & 0x1)) {
|
||||
(compmask & 0x1)) {
|
||||
vinterp[loc / 16] |= INTERP_ZERO << ((loc % 16) * 2);
|
||||
} else {
|
||||
vinterp[loc / 16] |= INTERP_FLAT << ((loc % 16) * 2);
|
||||
|
|
|
|||
|
|
@ -52,6 +52,12 @@ struct fd6_program_state {
|
|||
|
||||
const struct ir3_stream_output_info *stream_output;
|
||||
|
||||
/**
|
||||
* Whether multiple viewports are used is determined by whether
|
||||
* the last shader stage writes viewport id
|
||||
*/
|
||||
uint16_t num_viewports;
|
||||
|
||||
/**
|
||||
* Output components from frag shader. It is possible to have
|
||||
* a fragment shader that only writes a subset of the bound
|
||||
|
|
|
|||
|
|
@ -328,7 +328,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
|
|||
case PIPE_CAP_GLSL_FEATURE_LEVEL:
|
||||
case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
|
||||
if (is_a6xx(screen))
|
||||
return 400;
|
||||
return 430;
|
||||
else if (is_ir3(screen))
|
||||
return 140;
|
||||
else
|
||||
|
|
@ -396,6 +396,8 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
|
|||
return is_a6xx(screen);
|
||||
|
||||
case PIPE_CAP_MAX_VIEWPORTS:
|
||||
if (is_a6xx(screen))
|
||||
return 16;
|
||||
return 1;
|
||||
|
||||
case PIPE_CAP_MAX_VARYINGS:
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue