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winsys/amdgpu: add timeline point support to fence lists

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Add a parallel uint64_t *points array to amdgpu_fence_list to store
timeline semaphore point values alongside each fence. Point=0 means
binary semaphore (preserving existing behavior).

Update cs_add_fence_dependency and cs_add_syncobj_signal winsys
interfaces to accept a timeline_point parameter, and thread it
through to the fence lists. All existing callers pass 0.

Author: Claude Opus 4.6 <noreply@anthropic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40526>
This commit is contained in:
Qiang Yu 2026-03-19 17:14:33 +08:00 • committed by Marge Bot
parent 765a9f4fd9
commit c4edd58a74
5 changed files with 26 additions and 15 deletions
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4
src/gallium/drivers/radeonsi/si_fence.c
View file

@ -128,12 +128,12 @@ static void si_add_fence_dependency(struct si_context *sctx, struct pipe_fence_h
{
struct radeon_winsys *ws = sctx->ws;
ws->cs_add_fence_dependency(&sctx->gfx_cs, fence);
ws->cs_add_fence_dependency(&sctx->gfx_cs, fence, 0);
}
static void si_add_syncobj_signal(struct si_context *sctx, struct pipe_fence_handle *fence)
{
sctx->ws->cs_add_syncobj_signal(&sctx->gfx_cs, fence);
sctx->ws->cs_add_syncobj_signal(&sctx->gfx_cs, fence, 0);
}
static void si_fence_reference(struct pipe_screen *screen, struct pipe_fence_handle **dst,

6
src/gallium/include/winsys/radeon_winsys.h
View file

@ -702,12 +702,14 @@ struct radeon_winsys {
* Add a fence dependency to the CS, so that the CS will wait for
* the fence before execution.
*/
void (*cs_add_fence_dependency)(struct radeon_cmdbuf *rcs, struct pipe_fence_handle *fence);
void (*cs_add_fence_dependency)(struct radeon_cmdbuf *rcs, struct pipe_fence_handle *fence,
uint64_t timeline_point);
/**
* Signal a syncobj when the CS finishes execution.
*/
void (*cs_add_syncobj_signal)(struct radeon_cmdbuf *rcs, struct pipe_fence_handle *fence);
void (*cs_add_syncobj_signal)(struct radeon_cmdbuf *rcs, struct pipe_fence_handle *fence,
uint64_t timeline_point);
/**
* Returns the amd_ip_type type of a CS.

27
src/gallium/winsys/amdgpu/drm/amdgpu_cs.cpp
View file

@ -890,7 +890,9 @@ static void amdgpu_destroy_cs_context(struct amdgpu_winsys *aws, struct amdgpu_c
for (unsigned i = 0; i < ARRAY_SIZE(csc->buffer_lists); i++)
FREE(csc->buffer_lists[i].buffers);
FREE(csc->syncobj_dependencies.list);
FREE(csc->syncobj_dependencies.points);
FREE(csc->syncobj_to_signal.list);
FREE(csc->syncobj_to_signal.points);
}
@ -1205,23 +1207,27 @@ static unsigned amdgpu_cs_get_buffer_list(struct radeon_cmdbuf *rcs,
}
static void add_fence_to_list(struct amdgpu_fence_list *fences,
struct amdgpu_fence *fence)
struct amdgpu_fence *fence,
uint64_t point)
{
unsigned idx = fences->num++;
if (idx >= fences->max) {
unsigned size;
const unsigned increment = 8;
fences->max = idx + increment;
size = fences->max * sizeof(fences->list[0]);
fences->list = (struct pipe_fence_handle**)realloc(fences->list, size);
fences->list = (struct pipe_fence_handle**)realloc(fences->list,
fences->max * sizeof(fences->list[0]));
fences->points = (uint64_t*)realloc(fences->points,
fences->max * sizeof(fences->points[0]));
}
amdgpu_fence_set_reference(&fences->list[idx], (struct pipe_fence_handle*)fence);
fences->points[idx] = point;
}
static void amdgpu_cs_add_fence_dependency(struct radeon_cmdbuf *rcs,
struct pipe_fence_handle *pfence)
struct pipe_fence_handle *pfence,
uint64_t timeline_point)
{
struct amdgpu_cs *acs = amdgpu_cs(rcs);
struct amdgpu_winsys *aws = acs->aws;
@ -1241,7 +1247,7 @@ static void amdgpu_cs_add_fence_dependency(struct radeon_cmdbuf *rcs,
}
}
} else {
add_fence_to_list(&csc->syncobj_dependencies, fence);
add_fence_to_list(&csc->syncobj_dependencies, fence, timeline_point);
}
}
@ -1259,7 +1265,7 @@ static void amdgpu_add_fences_to_dependencies(struct amdgpu_winsys *ws,
}
if (bo->alt_fence)
add_fence_to_list(&csc->syncobj_dependencies, (struct amdgpu_fence*)bo->alt_fence);
add_fence_to_list(&csc->syncobj_dependencies, (struct amdgpu_fence*)bo->alt_fence, 0);
}
}
@ -1278,12 +1284,13 @@ static void amdgpu_add_to_kernel_bo_list(struct drm_amdgpu_bo_list_entry *bo_ent
}
static void amdgpu_cs_add_syncobj_signal(struct radeon_cmdbuf *rcs,
struct pipe_fence_handle *fence)
struct pipe_fence_handle *fence,
uint64_t timeline_point)
{
struct amdgpu_cs *acs = amdgpu_cs(rcs);
struct amdgpu_cs_context *csc = amdgpu_csc_get_current(acs);
add_fence_to_list(&csc->syncobj_to_signal, (struct amdgpu_fence*)fence);
add_fence_to_list(&csc->syncobj_to_signal, (struct amdgpu_fence*)fence, timeline_point);
}
static int amdgpu_cs_submit_ib_kernelq(struct amdgpu_cs *acs,
@ -2023,7 +2030,7 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index)
if (amdgpu_fence_wait(*fence, 0, false))
amdgpu_fence_reference(fence, NULL);
else
add_fence_to_list(&csc->syncobj_dependencies, (struct amdgpu_fence*)*fence);
add_fence_to_list(&csc->syncobj_dependencies, (struct amdgpu_fence*)*fence, 0);
}
}

1
src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
View file

@ -72,6 +72,7 @@ struct amdgpu_ib {
struct amdgpu_fence_list {
struct pipe_fence_handle **list;
uint64_t *points;
unsigned num;
unsigned max;
};

3
src/gallium/winsys/radeon/drm/radeon_drm_cs.c
View file

@ -831,7 +831,8 @@ static struct pipe_fence_handle *radeon_drm_cs_get_next_fence(struct radeon_cmdb
static void
radeon_drm_cs_add_fence_dependency(struct radeon_cmdbuf *rcs,
struct pipe_fence_handle *fence)
struct pipe_fence_handle *fence,
uint64_t timeline_point)
{
/* TODO: Handle the following unlikely multi-threaded scenario:
*