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i965/gen8: Correct HALIGN for AUX surfaces

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This restriction was attempted in this commit:
commit 4705346463
Author: Anuj Phogat <anuj.phogat@gmail.com>
Date:   Fri Feb 13 11:21:21 2015 -0800

   i965/gen8: Use HALIGN_16 if MCS is enabled for non-MSRT

However, the commit itself doesn't achieve the desired goal as determined by the
asserts which the next patch adds. mcs_mt is NULL (never set) we're in the
process of allocating the mcs_mt miptree when we get to this function. I didn't
check, but perhaps this would work with blorp, however, meta clears allocate the
miptree structure (which AFAICT needs the alignment also) way before it
allocates using meta clears where the renderbuffer is allocated way before the
aux buffer.

The restriction is referenced in a few places, but the most concise one [IMO]
from the spec is for Gen9. Gen8 loosens the restriction in that it only requires
this for non-msrt surface.

   When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN 16 must
   be used.

With the code before the miptree layout flag rework (patches preceding this),
accomplishing this workaround is very difficult.

v2:
bugfix: Don't set HALIGN16 for gens before 8 (Chad)

v3:
non-trivial rebase

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Cc: Neil Roberts <neil@linux.intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
This commit is contained in:
Ben Widawsky 2015-05-14 09:30:02 -07:00
parent e92fbdcf9c
commit c4aa041a61
3 changed files with 22 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
src/mesa/drivers/dri/i965/brw_tex_layout.c
View file

@ -116,8 +116,12 @@ tr_mode_horizontal_texture_alignment(const struct brw_context *brw,
static unsigned int
intel_horizontal_texture_alignment_unit(struct brw_context *brw,
struct intel_mipmap_tree *mt)
struct intel_mipmap_tree *mt,
uint32_t layout_flags)
{
if (layout_flags & MIPTREE_LAYOUT_FORCE_HALIGN16)
return 16;
/**
* From the "Alignment Unit Size" section of various specs, namely:
* - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
@ -172,9 +176,6 @@ intel_horizontal_texture_alignment_unit(struct brw_context *brw,
if (brw->gen >= 7 && mt->format == MESA_FORMAT_Z_UNORM16)
return 8;
if (brw->gen == 8 && mt->mcs_mt && mt->num_samples <= 1)
return 16;
return 4;
}
@ -792,6 +793,7 @@ brw_miptree_layout(struct brw_context *brw,
*/
mt->align_w = 64;
mt->align_h = 64;
assert((layout_flags & MIPTREE_LAYOUT_FORCE_HALIGN16) == 0);
} else {
/* Depth uses Y tiling, so we force need Y tiling alignment for the
* ALL_SLICES_AT_EACH_LOD miptree layout.
@ -800,7 +802,8 @@ brw_miptree_layout(struct brw_context *brw,
mt->align_h = 32;
}
} else {
mt->align_w = intel_horizontal_texture_alignment_unit(brw, mt);
mt->align_w =
intel_horizontal_texture_alignment_unit(brw, mt, layout_flags);
mt->align_h = intel_vertical_texture_alignment_unit(brw, mt);
}

15
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
View file

@ -489,6 +489,11 @@ intel_miptree_create_layout(struct brw_context *brw,
if (layout_flags & MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD)
mt->array_layout = ALL_SLICES_AT_EACH_LOD;
/* Use HALIGN_16 if MCS is enabled for non-MSRT */
if (brw->gen >= 8 && num_samples < 2 &&
intel_miptree_is_fast_clear_capable(brw, mt))
layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
brw_miptree_layout(brw, mt, requested, layout_flags);
if (mt->disable_aux_buffers)
@ -626,6 +631,7 @@ intel_miptree_create(struct brw_context *brw,
if (mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
assert(mt->num_samples > 1);
if (!intel_miptree_alloc_mcs(brw, mt, num_samples)) {
intel_miptree_release(&mt);
return NULL;
@ -638,8 +644,10 @@ intel_miptree_create(struct brw_context *brw,
* clear actually occurs.
*/
if (intel_tiling_supports_non_msrt_mcs(brw, mt->tiling) &&
intel_miptree_is_fast_clear_capable(brw, mt))
intel_miptree_is_fast_clear_capable(brw, mt)) {
mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
assert(brw->gen < 8 || mt->align_w == 16 || num_samples <= 1);
}
return mt;
}
@ -1357,6 +1365,9 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
unsigned mcs_height =
ALIGN(mt->logical_height0, height_divisor) / height_divisor;
assert(mt->logical_depth0 == 1);
uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
if (brw->gen >= 8)
layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
mt->mcs_mt = intel_miptree_create(brw,
mt->target,
format,
@ -1367,7 +1378,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
mt->logical_depth0,
0 /* num_samples */,
INTEL_MIPTREE_TILING_Y,
MIPTREE_LAYOUT_ACCELERATED_UPLOAD);
layout_flags);
return mt->mcs_mt;
}

1
src/mesa/drivers/dri/i965/intel_mipmap_tree.h
View file

@ -540,6 +540,7 @@ enum {
MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD = 1 << 1,
MIPTREE_LAYOUT_FOR_BO = 1 << 2,
MIPTREE_LAYOUT_DISABLE_AUX = 1 << 3,
MIPTREE_LAYOUT_FORCE_HALIGN16 = 1 << 4,
};
struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,