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freedreno/a5xx: Set num_sp_cores and set PC/VFD_POWER_CNTL accordingly.
Based on libwrap tracing of the blob. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>
This commit is contained in:
parent
c9f9d71412
commit
c4874b4cee
2 changed files with 35 additions and 5 deletions
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@ -232,8 +232,36 @@ add_gpus([
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GPUId(506),
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GPUId(506),
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GPUId(508),
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GPUId(508),
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GPUId(509),
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GPUId(509),
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], GPUInfo(
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CHIP.A5XX,
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gmem_align_w = 64, gmem_align_h = 32,
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tile_align_w = 64, tile_align_h = 32,
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tile_max_w = 1024, # max_bitfield_val(7, 0, 5)
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tile_max_h = max_bitfield_val(16, 9, 5),
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num_vsc_pipes = 16,
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cs_shared_mem_size = 32 * 1024,
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num_sp_cores = 1,
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wave_granularity = 2,
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fibers_per_sp = 64 * 16, # Lowest number that didn't fault on spillall fs-varying-array-mat4-col-row-rd.
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))
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add_gpus([
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GPUId(510),
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GPUId(510),
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GPUId(512),
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GPUId(512),
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], GPUInfo(
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CHIP.A5XX,
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gmem_align_w = 64, gmem_align_h = 32,
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tile_align_w = 64, tile_align_h = 32,
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tile_max_w = 1024, # max_bitfield_val(7, 0, 5)
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tile_max_h = max_bitfield_val(16, 9, 5),
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num_vsc_pipes = 16,
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cs_shared_mem_size = 32 * 1024,
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num_sp_cores = 2,
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wave_granularity = 2,
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fibers_per_sp = 64 * 16, # Lowest number that didn't fault on spillall fs-varying-array-mat4-col-row-rd.
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))
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add_gpus([
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GPUId(530),
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GPUId(530),
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GPUId(540),
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GPUId(540),
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], GPUInfo(
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], GPUInfo(
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@ -244,7 +272,7 @@ add_gpus([
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tile_max_h = max_bitfield_val(16, 9, 5),
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tile_max_h = max_bitfield_val(16, 9, 5),
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num_vsc_pipes = 16,
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num_vsc_pipes = 16,
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cs_shared_mem_size = 32 * 1024,
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cs_shared_mem_size = 32 * 1024,
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num_sp_cores = 0, # TODO
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num_sp_cores = 4,
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wave_granularity = 2,
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wave_granularity = 2,
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fibers_per_sp = 0, # TODO
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fibers_per_sp = 0, # TODO
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))
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))
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@ -394,6 +394,7 @@ emit_binning_pass(struct fd_batch *batch) assert_dt
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static void
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static void
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fd5_emit_tile_init(struct fd_batch *batch) assert_dt
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fd5_emit_tile_init(struct fd_batch *batch) assert_dt
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{
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{
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struct fd_context *ctx = batch->ctx;
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struct fd_ringbuffer *ring = batch->gmem;
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struct fd_ringbuffer *ring = batch->gmem;
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struct pipe_framebuffer_state *pfb = &batch->framebuffer;
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struct pipe_framebuffer_state *pfb = &batch->framebuffer;
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@ -411,10 +412,10 @@ fd5_emit_tile_init(struct fd_batch *batch) assert_dt
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OUT_RING(ring, 0x0);
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OUT_RING(ring, 0x0);
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OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1);
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OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1);
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OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */
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OUT_RING(ring, ctx->screen->info->num_sp_cores - 1); /* PC_POWER_CNTL */
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OUT_PKT4(ring, REG_A5XX_VFD_POWER_CNTL, 1);
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OUT_PKT4(ring, REG_A5XX_VFD_POWER_CNTL, 1);
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OUT_RING(ring, 0x00000003); /* VFD_POWER_CNTL */
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OUT_RING(ring, ctx->screen->info->num_sp_cores - 1); /* VFD_POWER_CNTL */
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/* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
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/* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
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fd_wfi(batch, ring);
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fd_wfi(batch, ring);
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@ -715,6 +716,7 @@ fd5_emit_tile_fini(struct fd_batch *batch) assert_dt
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static void
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static void
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fd5_emit_sysmem_prep(struct fd_batch *batch) assert_dt
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fd5_emit_sysmem_prep(struct fd_batch *batch) assert_dt
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{
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{
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struct fd_context *ctx = batch->ctx;
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struct fd_ringbuffer *ring = batch->gmem;
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struct fd_ringbuffer *ring = batch->gmem;
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fd5_emit_restore(batch, ring);
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fd5_emit_restore(batch, ring);
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@ -730,10 +732,10 @@ fd5_emit_sysmem_prep(struct fd_batch *batch) assert_dt
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fd5_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
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fd5_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
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OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1);
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OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1);
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OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */
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OUT_RING(ring, ctx->screen->info->num_sp_cores - 1); /* PC_POWER_CNTL */
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OUT_PKT4(ring, REG_A5XX_VFD_POWER_CNTL, 1);
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OUT_PKT4(ring, REG_A5XX_VFD_POWER_CNTL, 1);
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OUT_RING(ring, 0x00000003); /* VFD_POWER_CNTL */
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OUT_RING(ring, ctx->screen->info->num_sp_cores - 1); /* VFD_POWER_CNTL */
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/* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
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/* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
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fd_wfi(batch, ring);
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fd_wfi(batch, ring);
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