diff --git a/src/gallium/drivers/r600/evergreen_compute.c b/src/gallium/drivers/r600/evergreen_compute.c index a39208d6d24..fa36b4c979b 100644 --- a/src/gallium/drivers/r600/evergreen_compute.c +++ b/src/gallium/drivers/r600/evergreen_compute.c @@ -79,7 +79,6 @@ static void evergreen_set_rat(struct r600_pipe_compute *pipe, int size) { struct pipe_surface rat_templ; - struct r600_surface *surf = NULL; struct r600_context *rctx = NULL; assert(id < 12); @@ -98,12 +97,8 @@ static void evergreen_set_rat(struct r600_pipe_compute *pipe, rat_templ.first_layer = 0; rat_templ.last_layer = 0; - /* Add the RAT the list of color buffers. Drop the old buffer first. */ + /* Add the RAT the list of color buffers. */ pipe->ctx->framebuffer.state.cbufs[id] = rat_templ; - pipe_surface_unref(&pipe->ctx->b.b, &pipe->ctx->framebuffer.fb_cbufs[id]); - pipe->ctx->framebuffer.fb_cbufs[id] = pipe->ctx->b.b.create_surface( - (struct pipe_context *)pipe->ctx, - (struct pipe_resource *)bo, &rat_templ); /* Update the number of color buffers */ pipe->ctx->framebuffer.state.nr_cbufs = @@ -115,8 +110,9 @@ static void evergreen_set_rat(struct r600_pipe_compute *pipe, * of this driver. */ pipe->ctx->compute_cb_target_mask |= (0xf << (id * 4)); - surf = (struct r600_surface*)pipe->ctx->framebuffer.fb_cbufs[id]; - evergreen_init_color_surface_rat(rctx, &pipe->ctx->b.framebuffer.cbufs[id], surf); + evergreen_init_color_surface_rat(rctx, + &pipe->ctx->b.framebuffer.cbufs[id], + &pipe->ctx->framebuffer.state.cbufs[id]); } static void evergreen_cs_set_vertex_buffer(struct r600_context *rctx, diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 0fb178de470..f18fc96f87e 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -1304,13 +1304,13 @@ static void evergreen_set_color_surface_common(struct r600_context *rctx, */ void evergreen_init_color_surface_rat(struct r600_context *rctx, struct r600_cb_surface *cbuf, - const struct r600_surface *surf) + const struct pipe_surface *surf) { - struct pipe_resource *pipe_buffer = surf->base.texture; + struct pipe_resource *pipe_buffer = surf->texture; struct r600_tex_color_info color; evergreen_set_color_surface_buffer(rctx, r600_as_resource(pipe_buffer), - surf->base.format, 0, pipe_buffer->width0, + surf->format, 0, pipe_buffer->width0, &color); cbuf->cb_color_base = color.offset; @@ -1333,16 +1333,16 @@ void evergreen_init_color_surface_rat(struct r600_context *rctx, void evergreen_init_color_surface(struct r600_context *rctx, struct r600_cb_surface *surf, - const struct r600_surface *cbuf) + const struct pipe_surface *cbuf) { - struct r600_texture *rtex = r600_as_texture(cbuf->base.texture); - unsigned level = cbuf->base.level; + struct r600_texture *rtex = r600_as_texture(cbuf->texture); + unsigned level = cbuf->level; struct r600_tex_color_info color; evergreen_set_color_surface_common(rctx, rtex, level, - cbuf->base.first_layer, - cbuf->base.last_layer, - cbuf->base.format, + cbuf->first_layer, + cbuf->last_layer, + cbuf->format, &color); surf->alphatest_bypass = color.ntype == V_028C70_NUMBER_UINT || @@ -1363,18 +1363,18 @@ void evergreen_init_color_surface(struct r600_context *rctx, static void evergreen_init_depth_surface(struct r600_context *rctx, struct r600_cb_surface *surf, - const struct r600_surface *zbuf) + const struct pipe_surface *zbuf) { struct r600_screen *rscreen = rctx->screen; - struct r600_texture *rtex = r600_as_texture(zbuf->base.texture); - unsigned level = zbuf->base.level; + struct r600_texture *rtex = r600_as_texture(zbuf->texture); + unsigned level = zbuf->level; struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level]; uint64_t offset; unsigned format, array_mode; unsigned macro_aspect, tile_split, bankh, bankw, nbanks; - format = r600_translate_dbformat(zbuf->base.format); + format = r600_translate_dbformat(zbuf->format); assert(format != ~0); offset = rtex->resource.gpu_address; @@ -1415,8 +1415,8 @@ static void evergreen_init_depth_surface(struct r600_context *rctx, assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0); surf->db_depth_base = offset; - surf->db_depth_view = S_028008_SLICE_START(zbuf->base.first_layer) | - S_028008_SLICE_MAX(zbuf->base.last_layer); + surf->db_depth_view = S_028008_SLICE_START(zbuf->first_layer) | + S_028008_SLICE_MAX(zbuf->last_layer); surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) | S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1); surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x * @@ -1454,7 +1454,7 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx, const struct pipe_framebuffer_state *state) { struct r600_context *rctx = (struct r600_context *)ctx; - struct r600_surface *surf; + struct pipe_surface *surf; struct r600_texture *rtex; uint32_t i, log_samples; uint32_t target_mask = 0; @@ -1470,7 +1470,6 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx, R600_CONTEXT_FLUSH_AND_INV_DB_META | R600_CONTEXT_INV_TEX_CACHE; - util_framebuffer_init(ctx, state, rctx->framebuffer.fb_cbufs, &rctx->framebuffer.fb_zsbuf); util_copy_framebuffer_state(&rctx->framebuffer.state, state); /* Colorbuffers. */ @@ -1481,13 +1480,13 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx, rctx->cb_state.nr_samples = util_framebuffer_get_num_samples(state); for (i = 0; i < state->nr_cbufs; i++) { - surf = (struct r600_surface*)rctx->framebuffer.fb_cbufs[i]; - if (!surf) + surf = &rctx->framebuffer.state.cbufs[i]; + if (!surf->texture) continue; target_mask |= (0xf << (i * 4)); - rtex = r600_as_texture(surf->base.texture); + rtex = r600_as_texture(surf->texture); r600_context_add_resource_size(ctx, state->cbufs[i].texture); @@ -1510,8 +1509,8 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx, bool alphatest_bypass = false; bool export_16bpc = true; - surf = (struct r600_surface*)rctx->framebuffer.fb_cbufs[0]; - if (surf) { + surf = &rctx->framebuffer.state.cbufs[0]; + if (surf->texture) { alphatest_bypass = rctx->b.framebuffer.cbufs[0].alphatest_bypass; export_16bpc = rctx->b.framebuffer.cbufs[0].export_16bpc; } @@ -1528,7 +1527,7 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx, /* ZS buffer. */ if (state->zsbuf.texture) { - surf = (struct r600_surface*)rctx->framebuffer.fb_zsbuf; + surf = &rctx->framebuffer.state.zsbuf; r600_context_add_resource_size(ctx, state->zsbuf.texture); @@ -1539,11 +1538,9 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx, r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom); } - if (rctx->db_state.rsurf != surf) { - rctx->db_state.rsurf = surf; - r600_mark_atom_dirty(rctx, &rctx->db_state.atom); - r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom); - } + rctx->db_state.rsurf = surf; + r600_mark_atom_dirty(rctx, &rctx->db_state.atom); + r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom); } else if (rctx->db_state.rsurf) { rctx->db_state.rsurf = NULL; r600_mark_atom_dirty(rctx, &rctx->db_state.atom); @@ -1961,18 +1958,18 @@ static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r for (i = 0; i < nr_cbufs; i++) { unsigned reloc, cmask_reloc; - struct r600_surface *cbuf = (struct r600_surface*)rctx->framebuffer.fb_cbufs[i]; + struct pipe_surface *cbuf = &rctx->framebuffer.state.cbufs[i]; cb = &rctx->b.framebuffer.cbufs[i]; - if (!cbuf) { + if (!cbuf->texture) { radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, S_028C70_FORMAT(V_028C70_COLOR_INVALID)); continue; } - tex = r600_as_texture(cbuf->base.texture); + tex = r600_as_texture(cbuf->texture); reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, - r600_as_resource(cbuf->base.texture), + r600_as_resource(cbuf->texture), RADEON_USAGE_READWRITE | (tex->resource.b.b.nr_samples > 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA : @@ -2027,13 +2024,13 @@ static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r /* ZS buffer. */ if (state->zsbuf.texture) { - struct r600_surface *zsbuf = (struct r600_surface*)rctx->framebuffer.fb_zsbuf; + struct pipe_surface *zsbuf = &rctx->framebuffer.state.zsbuf; struct r600_cb_surface *zb = &rctx->b.framebuffer.zsbuf; unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, r600_as_resource(state->zsbuf.texture), RADEON_USAGE_READWRITE | - (zsbuf->base.texture->nr_samples > 1 ? + (zsbuf->texture->nr_samples > 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA : RADEON_PRIO_DEPTH_BUFFER)); @@ -2158,7 +2155,7 @@ static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom struct r600_db_state *a = (struct r600_db_state*)atom; if (a->rsurf && rctx->b.framebuffer.zsbuf.db_htile_surface) { - struct r600_texture *rtex = r600_as_texture(a->rsurf->base.texture); + struct r600_texture *rtex = r600_as_texture(a->rsurf->texture); unsigned reloc_idx; radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value)); diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c index 2c4374cd548..c18c9e7b025 100644 --- a/src/gallium/drivers/r600/r600_blit.c +++ b/src/gallium/drivers/r600/r600_blit.c @@ -515,7 +515,7 @@ evergreen_do_fast_color_clear(struct r600_context *rctx, if (!(*buffers & clear_bit)) continue; - tex = r600_as_texture(rctx->framebuffer.fb_cbufs[i]->texture); + tex = r600_as_texture(rctx->framebuffer.state.cbufs[i].texture); /* the clear is allowed if all layers are bound */ if (fb->cbufs[i].first_layer != 0 || diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index 0ebadcbe7bb..481b8630966 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -75,7 +75,6 @@ static void r600_destroy_context(struct pipe_context *context) if (rctx->custom_blend_fastclear) { rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear); } - util_framebuffer_init(context, NULL, rctx->framebuffer.fb_cbufs, &rctx->framebuffer.fb_zsbuf); util_unreference_framebuffer_state(&rctx->framebuffer.state); if (rctx->gs_rings.gsvs_ring.buffer) diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h index d5192a43ab2..801a7db32bd 100644 --- a/src/gallium/drivers/r600/r600_pipe.h +++ b/src/gallium/drivers/r600/r600_pipe.h @@ -111,7 +111,7 @@ struct r600_command_buffer { struct r600_db_state { struct r600_atom atom; - struct r600_surface *rsurf; + struct pipe_surface *rsurf; }; struct r600_db_misc_state { @@ -188,7 +188,6 @@ struct r600_cs_shader_state { }; struct r600_framebuffer { - PIPE_FB_SURFACES; //STOP USING THIS struct pipe_framebuffer_state state; }; @@ -723,10 +722,10 @@ bool evergreen_is_format_supported(struct pipe_screen *screen, unsigned usage); void evergreen_init_color_surface(struct r600_context *rctx, struct r600_cb_surface *surf, - const struct r600_surface *cbuf); + const struct pipe_surface *cbuf); void evergreen_init_color_surface_rat(struct r600_context *rctx, struct r600_cb_surface *surf, - const struct r600_surface *cbuf); + const struct pipe_surface *cbuf); void evergreen_update_db_shader_control(struct r600_context * rctx); bool evergreen_adjust_gprs(struct r600_context *rctx); void evergreen_setup_scratch_buffers(struct r600_context *rctx); diff --git a/src/gallium/drivers/r600/r600_pipe_common.h b/src/gallium/drivers/r600/r600_pipe_common.h index 90944e3659a..ce4803fa701 100644 --- a/src/gallium/drivers/r600/r600_pipe_common.h +++ b/src/gallium/drivers/r600/r600_pipe_common.h @@ -234,10 +234,6 @@ struct r600_texture { uint32_t framebuffers_bound; }; -struct r600_surface { - struct pipe_surface base; -}; - struct r600_cb_surface { /* Misc. color flags. */ bool alphatest_bypass; diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 9c9ddcde1f3..e464f91700c 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -801,12 +801,12 @@ static void r600_set_polygon_stipple(struct pipe_context *ctx, static void r600_init_color_surface(struct r600_context *rctx, struct r600_pre_eg_cb *surf, - const struct r600_surface *cbuf, + const struct pipe_surface *cbuf, bool force_cmask_fmask) { struct r600_screen *rscreen = rctx->screen; - struct r600_texture *rtex = r600_as_texture(cbuf->base.texture); - unsigned level = cbuf->base.level; + struct r600_texture *rtex = r600_as_texture(cbuf->texture); + unsigned level = cbuf->level; unsigned pitch, slice; unsigned color_info; unsigned color_view; @@ -817,14 +817,14 @@ static void r600_init_color_surface(struct r600_context *rctx, bool blend_bypass = 0, blend_clamp = 0, do_endian_swap = false; if (rtex->db_compatible && !r600_can_sample_zs(rtex, false)) { - r600_init_flushed_depth_texture(&rctx->b.b, cbuf->base.texture, NULL); + r600_init_flushed_depth_texture(&rctx->b.b, cbuf->texture, NULL); rtex = rtex->flushed_depth_texture; assert(rtex); } offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256; - color_view = S_028080_SLICE_START(cbuf->base.first_layer) | - S_028080_SLICE_MAX(cbuf->base.last_layer); + color_view = S_028080_SLICE_START(cbuf->first_layer) | + S_028080_SLICE_MAX(cbuf->last_layer); pitch = rtex->surface.u.legacy.level[level].nblk_x / 8 - 1; slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64; @@ -845,9 +845,9 @@ static void r600_init_color_surface(struct r600_context *rctx, break; } - desc = util_format_description(cbuf->base.format); + desc = util_format_description(cbuf->format); - i = util_format_get_first_non_void_channel(cbuf->base.format); + i = util_format_get_first_non_void_channel(cbuf->format); ntype = V_0280A0_NUMBER_UNORM; if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) @@ -869,11 +869,11 @@ static void r600_init_color_surface(struct r600_context *rctx, if (UTIL_ARCH_BIG_ENDIAN) do_endian_swap = !rtex->db_compatible; - format = r600_translate_colorformat(rctx->b.gfx_level, cbuf->base.format, + format = r600_translate_colorformat(rctx->b.gfx_level, cbuf->format, do_endian_swap); assert(format != ~0); - swap = r600_translate_colorswap(cbuf->base.format, do_endian_swap); + swap = r600_translate_colorswap(cbuf->format, do_endian_swap); assert(swap != ~0); endian = r600_colorformat_endian_swap(format, do_endian_swap); @@ -1027,12 +1027,12 @@ static void r600_init_color_surface(struct r600_context *rctx, static void r600_init_depth_surface(struct r600_context *rctx, struct r600_pre_eg_zs *surf, - const struct r600_surface *zbuf) + const struct pipe_surface *zbuf) { - struct r600_texture *rtex = r600_as_texture(zbuf->base.texture); + struct r600_texture *rtex = r600_as_texture(zbuf->texture); unsigned level, pitch, slice, format, offset, array_mode; - level = zbuf->base.level; + level = zbuf->level; offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256; pitch = rtex->surface.u.legacy.level[level].nblk_x / 8 - 1; slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64; @@ -1050,13 +1050,13 @@ static void r600_init_depth_surface(struct r600_context *rctx, break; } - format = r600_translate_dbformat(zbuf->base.format); + format = r600_translate_dbformat(zbuf->format); assert(format != ~0); surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format); surf->db_depth_base = offset >> 8; - surf->db_depth_view = S_028004_SLICE_START(zbuf->base.first_layer) | - S_028004_SLICE_MAX(zbuf->base.last_layer); + surf->db_depth_view = S_028004_SLICE_START(zbuf->first_layer) | + S_028004_SLICE_MAX(zbuf->last_layer); surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice); surf->db_prefetch_limit = (rtex->surface.u.legacy.level[level].nblk_y / 8) - 1; @@ -1074,7 +1074,7 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx, const struct pipe_framebuffer_state *state) { struct r600_context *rctx = (struct r600_context *)ctx; - struct r600_surface *surf; + struct pipe_surface *surf; struct r600_texture *rtex; unsigned i; uint32_t target_mask = 0; @@ -1092,7 +1092,6 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx, R600_CONTEXT_INV_TEX_CACHE; /* Set the new state. */ - util_framebuffer_init(ctx, state, rctx->framebuffer.fb_cbufs, &rctx->framebuffer.fb_zsbuf); util_copy_framebuffer_state(&rctx->framebuffer.state, state); rctx->cb_state.export_16bpc = state->nr_cbufs != 0; @@ -1112,11 +1111,11 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx, rctx->cb_state.is_msaa_resolve && i == 1; - surf = (struct r600_surface*)rctx->framebuffer.fb_cbufs[i]; - if (!surf) + surf = &rctx->framebuffer.state.cbufs[i]; + if (!surf->texture) continue; - rtex = r600_as_texture(surf->base.texture); + rtex = r600_as_texture(surf->texture); r600_context_add_resource_size(ctx, state->cbufs[i].texture); struct r600_pre_eg_cb *const cb = &rctx->b.r600_pre_eg_cbzs->cb_surface[i]; @@ -1139,8 +1138,8 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx, if (state->nr_cbufs) { bool alphatest_bypass = false; - surf = (struct r600_surface*)rctx->framebuffer.fb_cbufs[0]; - if (surf) { + surf = &rctx->framebuffer.state.cbufs[0]; + if (surf->texture) { alphatest_bypass = rctx->b.r600_pre_eg_cbzs->cb_surface[0].alphatest_bypass; } @@ -1152,7 +1151,7 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx, /* ZS buffer. */ if (state->zsbuf.texture) { - surf = (struct r600_surface*)rctx->framebuffer.fb_zsbuf; + surf = &rctx->framebuffer.state.zsbuf; r600_context_add_resource_size(ctx, state->zsbuf.texture); @@ -1165,11 +1164,9 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx, r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom); } - if (rctx->db_state.rsurf != surf) { - rctx->db_state.rsurf = surf; - r600_mark_atom_dirty(rctx, &rctx->db_state.atom); - r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom); - } + rctx->db_state.rsurf = surf; + r600_mark_atom_dirty(rctx, &rctx->db_state.atom); + r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom); } else if (rctx->db_state.rsurf) { rctx->db_state.rsurf = NULL; r600_mark_atom_dirty(rctx, &rctx->db_state.atom); @@ -1341,17 +1338,17 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a struct pipe_framebuffer_state *state = &rctx->framebuffer.state; unsigned nr_cbufs = state->nr_cbufs; - struct r600_surface **cbuf = (struct r600_surface**)&rctx->framebuffer.fb_cbufs[0]; + const struct pipe_surface *cbuf = &rctx->framebuffer.state.cbufs[0]; struct r600_pre_eg_cb *const cb = &rctx->b.r600_pre_eg_cbzs->cb_surface[0]; struct r600_pre_eg_zs *const zs = &rctx->b.r600_pre_eg_cbzs->zs_surface; /* Colorbuffers. */ radeon_set_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8); for (i = 0; i < nr_cbufs; i++) { - radeon_emit(cs, cbuf[i] ? cb[i].cb_color_info : 0); + radeon_emit(cs, cbuf[i].texture ? cb[i].cb_color_info : 0); } /* set CB_COLOR1_INFO for possible dual-src blending */ - if (rctx->cb_state.dual_src_blend && i == 1 && cbuf[0]) { + if (rctx->cb_state.dual_src_blend && i == 1 && cbuf[0].texture) { radeon_emit(cs, cb[0].cb_color_info); i++; } @@ -1363,7 +1360,7 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a for (i = 0; i < nr_cbufs; i++) { unsigned reloc; - if (!cbuf[i]) + if (!cbuf[i].texture) continue; /* COLOR_BASE */ @@ -1371,9 +1368,9 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, - r600_as_resource(cbuf[i]->base.texture), + r600_as_resource(cbuf[i].texture), RADEON_USAGE_READWRITE | - (cbuf[i]->base.texture->nr_samples > 1 ? + (cbuf[i].texture->nr_samples > 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA : RADEON_PRIO_COLOR_BUFFER)); radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); @@ -1386,7 +1383,7 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a &rctx->b.gfx, cb[i].cb_buffer_fmask, RADEON_USAGE_READWRITE | - (cbuf[i]->base.texture->nr_samples > 1 ? + (cbuf[i].texture->nr_samples > 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA : RADEON_PRIO_COLOR_BUFFER)); radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); @@ -1399,7 +1396,7 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a &rctx->b.gfx, cb[i].cb_buffer_cmask, RADEON_USAGE_READWRITE | - (cbuf[i]->base.texture->nr_samples > 1 ? + (cbuf[i].texture->nr_samples > 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA : RADEON_PRIO_COLOR_BUFFER)); radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); @@ -1408,17 +1405,17 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a radeon_set_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs); for (i = 0; i < nr_cbufs; i++) { - radeon_emit(cs, cbuf[i] ? cb[i].cb_color_size : 0); + radeon_emit(cs, cbuf[i].texture ? cb[i].cb_color_size : 0); } radeon_set_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs); for (i = 0; i < nr_cbufs; i++) { - radeon_emit(cs, cbuf[i] ? cb[i].cb_color_view : 0); + radeon_emit(cs, cbuf[i].texture ? cb[i].cb_color_view : 0); } radeon_set_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs); for (i = 0; i < nr_cbufs; i++) { - radeon_emit(cs, cbuf[i] ? cb[i].cb_color_mask : 0); + radeon_emit(cs, cbuf[i].texture ? cb[i].cb_color_mask : 0); } sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs); @@ -1433,12 +1430,12 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a /* Zbuffer. */ if (state->zsbuf.texture) { - struct r600_surface *zsbuf = (struct r600_surface*)rctx->framebuffer.fb_zsbuf; + struct pipe_surface *zsbuf = &rctx->framebuffer.state.zsbuf; unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, r600_as_resource(state->zsbuf.texture), RADEON_USAGE_READWRITE | - (zsbuf->base.texture->nr_samples > 1 ? + (zsbuf->texture->nr_samples > 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA : RADEON_PRIO_DEPTH_BUFFER)); @@ -1537,7 +1534,7 @@ static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom struct r600_db_state *a = (struct r600_db_state*)atom; if (a->rsurf && rctx->b.r600_pre_eg_cbzs->zs_surface.db_htile_surface) { - struct r600_texture *rtex = r600_as_texture(a->rsurf->base.texture); + struct r600_texture *rtex = r600_as_texture(a->rsurf->texture); unsigned reloc_idx; radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value)); diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c index 760fb2e6d33..96ca3639dc6 100644 --- a/src/gallium/drivers/r600/r600_state_common.c +++ b/src/gallium/drivers/r600/r600_state_common.c @@ -3014,7 +3014,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info do { unsigned i = u_bit_scan(&mask); - surf = rctx->framebuffer.fb_cbufs[i]; + surf = &rctx->framebuffer.state.cbufs[i]; rtex = r600_as_texture(surf->texture); rtex->dirty_level_mask |= 1 << surf->level; diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c index 5187907cc7b..5f28cff064f 100644 --- a/src/gallium/drivers/r600/r600_texture.c +++ b/src/gallium/drivers/r600/r600_texture.c @@ -1492,7 +1492,7 @@ struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe, const struct pipe_surface *templ, unsigned width0, unsigned height0) { - struct r600_surface *surface = CALLOC_STRUCT(r600_surface); + struct pipe_surface *surface = CALLOC_STRUCT(pipe_surface); if (!surface) return NULL; @@ -1500,15 +1500,15 @@ struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe, assert(templ->first_layer <= util_max_layer(texture, templ->level)); assert(templ->last_layer <= util_max_layer(texture, templ->level)); - pipe_reference_init(&surface->base.reference, 1); - pipe_resource_reference(&surface->base.texture, texture); - surface->base.context = pipe; - surface->base.format = templ->format; - surface->base.level = templ->level; - surface->base.first_layer = templ->first_layer; - surface->base.last_layer = templ->last_layer; + pipe_reference_init(&surface->reference, 1); + pipe_resource_reference(&surface->texture, texture); + surface->context = pipe; + surface->format = templ->format; + surface->level = templ->level; + surface->first_layer = templ->first_layer; + surface->last_layer = templ->last_layer; - return &surface->base; + return surface; } static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,