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asahi: Use PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY

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The hardware only supports aligned loads and stores. That applies to vertex
buffer loads as well. As such, we need to ensure that the base address of vertex
buffers, the stride, and the offset are all aligned to the vertex buffer format,
ensuring that the load itself is aligned. Mesa has a CAP for that,
PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY, which ensures that these conditions
are met and will rewrite a vertex buffer on the CPU in the off chance that
they're not.

This is a bug fix compared to the old code, because it requires that offsets and
base addresses are aligned (not just the strides like before). It's also an
optimization compared to the old code, because it does not require 4 byte
alignment for 8-bit and 16-bit formats. In fact, it doesn't require any
alignment for 8-bit formats. This will avoid needless CPU work for smaller
formats.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19996>
This commit is contained in:
Alyssa Rosenzweig 2022-11-30 12:51:41 -05:00 • committed by Marge Bot
parent 8dcf7648f1
commit c445c29263
1 changed files with 1 additions and 1 deletions
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2
src/gallium/drivers/asahi/agx_pipe.c
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@ -1318,7 +1318,7 @@ agx_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
return 64;
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY:
return 1;
case PIPE_CAP_MAX_TEXTURE_2D_SIZE: