diff --git a/src/intel/compiler/brw_nir_lower_rt_intrinsics.c b/src/intel/compiler/brw_nir_lower_rt_intrinsics.c index 441a21dc328..a5fed61ef59 100644 --- a/src/intel/compiler/brw_nir_lower_rt_intrinsics.c +++ b/src/intel/compiler/brw_nir_lower_rt_intrinsics.c @@ -88,6 +88,7 @@ lower_rt_intrinsics_impl(nir_function_impl *impl, nir_ssa_def *stack_base_addr = nir_iadd(b, thread_stack_base_addr, nir_u2u64(b, stack_base_offset)); ASSERTED bool seen_scratch_base_ptr_load = false; + ASSERTED bool found_resume = false; nir_foreach_block(block, impl) { nir_foreach_instr_safe(instr, block) { @@ -121,6 +122,7 @@ lower_rt_intrinsics_impl(nir_function_impl *impl, /* This is the first "interesting" instruction */ assert(block == nir_start_block(impl)); assert(!seen_scratch_base_ptr_load); + found_resume = true; int32_t stack_size = nir_intrinsic_range(intrin); if (stack_size > 0) { @@ -234,6 +236,17 @@ lower_rt_intrinsics_impl(nir_function_impl *impl, break; } + case nir_intrinsic_load_shader_record_ptr: + /* We can't handle this intrinsic in resume shaders because the + * handle we get there won't be from the original SBT. The shader + * call lowering/splitting pass should have ensured that this + * value was spilled from the initial shader and unspilled in any + * resume shaders that need it. + */ + assert(!found_resume); + sysval = nir_load_btd_local_arg_addr_intel(b); + break; + case nir_intrinsic_load_ray_base_mem_addr_intel: sysval = globals.base_mem_addr; break; diff --git a/src/intel/compiler/brw_nir_rt.c b/src/intel/compiler/brw_nir_rt.c index 6c9fd3a5d51..0c905a29f28 100644 --- a/src/intel/compiler/brw_nir_rt.c +++ b/src/intel/compiler/brw_nir_rt.c @@ -178,10 +178,12 @@ lower_rt_io_and_scratch(nir_shader *nir) /* Now patch any derefs to I/O vars */ NIR_PASS_V(nir, lower_rt_io_derefs); - /* Finally, lower any remaining function_temp access to 64-bit global - * memory access. + /* Finally, lower any remaining function_temp and mem_constant access to + * 64-bit global memory access. */ - NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_function_temp, + NIR_PASS_V(nir, nir_lower_explicit_io, + nir_var_function_temp | + nir_var_mem_constant, nir_address_format_64bit_global); }