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brw: Remove prefix gfx10 from enum types

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The values already use BRW, make it consistent.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33664>
This commit is contained in:
Caio Oliveira 2025-02-21 02:11:45 -08:00 • committed by Marge Bot
parent 9dfff2cb14
commit c3d2ba6973
4 changed files with 20 additions and 20 deletions
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8
src/intel/compiler/brw_disasm.c
View file

@ -954,7 +954,7 @@ dest(FILE *file, const struct brw_isa_info *isa, const brw_eu_inst *inst)
}
static enum brw_horizontal_stride
hstride_from_align1_3src_dst_hstride(enum gfx10_align1_3src_dst_horizontal_stride hstride)
hstride_from_align1_3src_dst_hstride(enum brw_align1_3src_dst_horizontal_stride hstride)
{
switch (hstride) {
case BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1: return BRW_HORIZONTAL_STRIDE_1;
@ -1176,7 +1176,7 @@ src_da16(FILE *file,
static enum brw_vertical_stride
vstride_from_align1_3src_vstride(const struct intel_device_info *devinfo,
enum gfx10_align1_3src_vertical_stride vstride)
enum brw_align1_3src_vertical_stride vstride)
{
switch (vstride) {
case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0: return BRW_VERTICAL_STRIDE_0;
@ -1193,7 +1193,7 @@ vstride_from_align1_3src_vstride(const struct intel_device_info *devinfo,
}
static enum brw_horizontal_stride
hstride_from_align1_3src_hstride(enum gfx10_align1_3src_src_horizontal_stride hstride)
hstride_from_align1_3src_hstride(enum brw_align1_3src_src_horizontal_stride hstride)
{
switch (hstride) {
case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0: return BRW_HORIZONTAL_STRIDE_0;
@ -1206,7 +1206,7 @@ hstride_from_align1_3src_hstride(enum gfx10_align1_3src_src_horizontal_stride hs
}
static enum brw_vertical_stride
vstride_from_align1_3src_hstride(enum gfx10_align1_3src_src_horizontal_stride hstride)
vstride_from_align1_3src_hstride(enum brw_align1_3src_src_horizontal_stride hstride)
{
switch (hstride) {
case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0: return BRW_VERTICAL_STRIDE_0;

10
src/intel/compiler/brw_eu_defines.h
View file

@ -115,14 +115,14 @@ enum ENUM_PACKED brw_horizontal_stride {
BRW_HORIZONTAL_STRIDE_4 = 3,
};
enum ENUM_PACKED gfx10_align1_3src_src_horizontal_stride {
enum ENUM_PACKED brw_align1_3src_src_horizontal_stride {
BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0 = 0,
BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1 = 1,
BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2 = 2,
BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4 = 3,
};
enum ENUM_PACKED gfx10_align1_3src_dst_horizontal_stride {
enum ENUM_PACKED brw_align1_3src_dst_horizontal_stride {
BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1 = 0,
BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_2 = 1,
};
@ -798,12 +798,12 @@ enum ENUM_PACKED brw_reg_file {
UNIFORM, /* prog_data->params[reg] */
};
/* CNL adds Align1 support for 3-src instructions. Bit 35 of the instruction
/* Align1 support for 3-src instructions. Bit 35 of the instruction
* word is "Execution Datatype" which controls whether the instruction operates
* on float or integer types. The register arguments have fields that offer
* more fine control their respective types.
*/
enum ENUM_PACKED gfx10_align1_3src_exec_type {
enum ENUM_PACKED brw_align1_3src_exec_type {
BRW_ALIGN1_3SRC_EXEC_TYPE_INT = 0,
BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT = 1,
};
@ -843,7 +843,7 @@ enum ENUM_PACKED brw_vertical_stride {
BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL = 0xF,
};
enum ENUM_PACKED gfx10_align1_3src_vertical_stride {
enum ENUM_PACKED brw_align1_3src_vertical_stride {
BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0 = 0,
BRW_ALIGN1_3SRC_VERTICAL_STRIDE_1 = 1,
BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2 = 1,

6
src/intel/compiler/brw_eu_emit.c
View file

@ -508,7 +508,7 @@ brw_alu2(struct brw_codegen *p, unsigned opcode,
return insn;
}
static enum gfx10_align1_3src_vertical_stride
static enum brw_align1_3src_vertical_stride
to_3src_align1_vstride(const struct intel_device_info *devinfo,
enum brw_vertical_stride vstride)
{
@ -531,7 +531,7 @@ to_3src_align1_vstride(const struct intel_device_info *devinfo,
}
}
static enum gfx10_align1_3src_dst_horizontal_stride
static enum brw_align1_3src_dst_horizontal_stride
to_3src_align1_dst_hstride(enum brw_horizontal_stride hstride)
{
switch (hstride) {
@ -544,7 +544,7 @@ to_3src_align1_dst_hstride(enum brw_horizontal_stride hstride)
}
}
static enum gfx10_align1_3src_src_horizontal_stride
static enum brw_align1_3src_src_horizontal_stride
to_3src_align1_hstride(enum brw_horizontal_stride hstride)
{
switch (hstride) {

16
src/intel/compiler/brw_eu_inst.h
View file

@ -532,8 +532,8 @@ brw_eu_inst_set_3src_a1_##reg##_type(const struct intel_device_info *devinfo, \
brw_eu_inst *inst, \
enum brw_reg_type type) \
{ \
UNUSED enum gfx10_align1_3src_exec_type exec_type = \
(enum gfx10_align1_3src_exec_type) \
UNUSED enum brw_align1_3src_exec_type exec_type = \
(enum brw_align1_3src_exec_type) \
brw_eu_inst_3src_a1_exec_type(devinfo, inst); \
if (brw_type_is_float(type)) { \
assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \
@ -548,8 +548,8 @@ static inline enum brw_reg_type \
brw_eu_inst_3src_a1_##reg##_type(const struct intel_device_info *devinfo, \
const brw_eu_inst *inst) \
{ \
enum gfx10_align1_3src_exec_type exec_type = \
(enum gfx10_align1_3src_exec_type) \
enum brw_align1_3src_exec_type exec_type = \
(enum brw_align1_3src_exec_type) \
brw_eu_inst_3src_a1_exec_type(devinfo, inst); \
unsigned hw_type = brw_eu_inst_3src_a1_##reg##_hw_type(devinfo, inst); \
return brw_type_decode_for_3src(devinfo, hw_type, exec_type); \
@ -643,8 +643,8 @@ brw_eu_inst_set_dpas_3src_##reg##_type(const struct intel_device_info *devinfo,
brw_eu_inst *inst, \
enum brw_reg_type type) \
{ \
UNUSED enum gfx10_align1_3src_exec_type exec_type = \
(enum gfx10_align1_3src_exec_type) \
UNUSED enum brw_align1_3src_exec_type exec_type = \
(enum brw_align1_3src_exec_type) \
brw_eu_inst_dpas_3src_exec_type(devinfo, inst); \
if (brw_type_is_float(type)) { \
assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \
@ -659,8 +659,8 @@ static inline enum brw_reg_type \
brw_eu_inst_dpas_3src_##reg##_type(const struct intel_device_info *devinfo, \
const brw_eu_inst *inst) \
{ \
enum gfx10_align1_3src_exec_type exec_type = \
(enum gfx10_align1_3src_exec_type) \
enum brw_align1_3src_exec_type exec_type = \
(enum brw_align1_3src_exec_type) \
brw_eu_inst_dpas_3src_exec_type(devinfo, inst); \
unsigned hw_type = brw_eu_inst_dpas_3src_##reg##_hw_type(devinfo, inst); \
return brw_type_decode_for_3src(devinfo, hw_type, exec_type); \