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radv: Fix L2 cache rinse programming.

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According to radeonsi, GLM doesn't support WB alone, so
we have to set INV too when WB is set.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Timur Kristóf 2019-09-26 09:37:16 +02:00 • committed by Bas Nieuwenhuizen
parent 8727253329
commit c372dc762d
1 changed files with 9 additions and 5 deletions
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14
src/amd/vulkan/si_cmd_buffer.c
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@ -886,15 +886,19 @@ gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
if (flush_bits & RADV_CMD_FLAG_INV_L2) {
/* Writeback and invalidate everything in L2. */
gcr_cntl |= S_586_GL2_INV(1) | S_586_GLM_INV(1);
gcr_cntl |= S_586_GL2_INV(1) | S_586_GL2_WB(1) |
S_586_GLM_INV(1) | S_586_GLM_WB(1);
} else if (flush_bits & RADV_CMD_FLAG_WB_L2) {
/* Writeback but do not invalidate. */
gcr_cntl |= S_586_GL2_WB(1);
/* Writeback but do not invalidate.
* GLM doesn't support WB alone. If WB is set, INV must be set too.
*/
gcr_cntl |= S_586_GL2_WB(1) |
S_586_GLM_WB(1) | S_586_GLM_INV(1);
}
/* TODO: Implement this new flag for GFX9+.
if (flush_bits & RADV_CMD_FLAG_INV_L2_METADATA)
gcr_cntl |= S_586_GLM_INV(1);
else if (flush_bits & RADV_CMD_FLAG_INV_L2_METADATA)
gcr_cntl |= S_586_GLM_INV(1) | S_586_GLM_WB(1);
*/
if (flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {