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i965/vec4: set correct register regions for 32-bit and 64-bit

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For 32-bit instructions we want to use <4,4,1> regions for VGRF
sources so we should really set a width of 4 (we were setting 8).

For 64-bit instructions we want to use a width of 2 because the
hardware uses 32-bit swizzles, meaning that we can only address 2
consecutive 64-bit components in a row. Also, Curro suggested that
the hardware is probably fixing the width to 2 for 64-bit instructions
anyway, so just go with that and use <2,2,1>.

v2:
 - No need to explicitly set the vertical stride of 64-bit regions to 2,
   brw_vecn_grf with a width of 2 will do that for us.
 - No need to adjust the width of dst registers.

v3 (Ian):
 - Make type_size and width const.

Signed-off-by: Connor Abbott <connor.w.abbott@intel.com>

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Iago Toral Quiroga 2015-11-18 14:00:58 +01:00 • committed by Samuel Iglesias Gonsálvez
parent ed74b19ab4
commit c35fa7ac55
1 changed files with 9 additions and 4 deletions
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13
src/mesa/drivers/dri/i965/brw_vec4.cpp
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@ -1873,20 +1873,24 @@ vec4_visitor::convert_to_hw_regs()
struct src_reg &src = inst->src[i]; struct src_reg &src = inst->src[i];
struct brw_reg reg; struct brw_reg reg;
switch (src.file) { switch (src.file) {
case VGRF: case VGRF: {
reg = byte_offset(brw_vec8_grf(src.nr, 0), src.offset); const unsigned type_size = type_sz(src.type);
const unsigned width = REG_SIZE / 2 / MAX2(4, type_size);
reg = byte_offset(brw_vecn_grf(width, src.nr, 0), src.offset);
reg.type = src.type; reg.type = src.type;
reg.swizzle = src.swizzle; reg.swizzle = src.swizzle;
reg.abs = src.abs; reg.abs = src.abs;
reg.negate = src.negate; reg.negate = src.negate;
break; break;
}
case UNIFORM: case UNIFORM: {
const unsigned width = REG_SIZE / 2 / MAX2(4, type_sz(src.type));
reg = stride(byte_offset(brw_vec4_grf( reg = stride(byte_offset(brw_vec4_grf(
prog_data->base.dispatch_grf_start_reg + prog_data->base.dispatch_grf_start_reg +
src.nr / 2, src.nr % 2 * 4), src.nr / 2, src.nr % 2 * 4),
src.offset), src.offset),
0, 4, 1); 0, width, 1);
reg.type = src.type; reg.type = src.type;
reg.swizzle = src.swizzle; reg.swizzle = src.swizzle;
reg.abs = src.abs; reg.abs = src.abs;
@ -1895,6 +1899,7 @@ vec4_visitor::convert_to_hw_regs()
/* This should have been moved to pull constants. */ /* This should have been moved to pull constants. */
assert(!src.reladdr); assert(!src.reladdr);
break; break;
}
case ARF: case ARF:
case FIXED_GRF: case FIXED_GRF: