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ac/gpu_info: update multimedia info

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update multimedia info to show num_instances and firmware version when valid
and video codec capabilities are shown if the query is supported and valid.
Multimedia info: from Navi21 ASIC is shown below.

Multimedia info:
    vcn_decode = 2
    vcn_encode = 2
    vcn_enc_major_version = 1
    vcn_enc_minor_version = 30
    vcn_dec_version = 3
    jpeg_decode = 1
    codec    dec  max_resolution   enc  max_resolution
    mpeg2    *    4096x4096        -    -
    mpeg4    *    4096x4096        -    -
    vc1      *    4096x4096        -    -
    h264     *    4096x4096        *    4096x2160
    hevc     *    8192x4352        *    7680x4352
    jpeg     *    4096x4096        -    -
    vp9      *    8192x4352        -    -
    av1      *    8192x4352        -    -

v2: fix build error with _WIN32 builds
v3: rebase on 76425cdf23 (ac/gpu_info: Add vcn dec and enc version query)

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28252>
This commit is contained in:
Sathishkumar S 2024-03-28 23:16:22 +05:30 • committed by Sathishkumar S
parent eb693cfec6
commit c34cfc1a3b
1 changed files with 85 additions and 33 deletions
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118
src/amd/common/ac_gpu_info.c
View file

@ -77,6 +77,16 @@
#define AMDGPU_VRAM_TYPE_LPDDR4 11
#define AMDGPU_VRAM_TYPE_LPDDR5 12
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8
struct drm_amdgpu_heap_info {
uint64_t total_heap_size;
};
@ -597,8 +607,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
struct amdgpu_gpu_info amdinfo;
struct drm_amdgpu_info_device device_info = {0};
struct amdgpu_buffer_size_alignments alignment_info = {0};
uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0,
vcn_version = 0, vcn_feature = 0;
uint32_t vidip_fw_version = 0, vidip_fw_feature = 0;
uint32_t num_instances = 0;
int r, i, j;
amdgpu_device_handle dev = dev_p;
@ -741,22 +750,30 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
return false;
}
r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_UVD, 0, 0, &uvd_version, &uvd_feature);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
return false;
}
r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_VCE, 0, 0, &vce_version, &vce_feature);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
return false;
}
r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_VCN, 0, 0, &vcn_version, &vcn_feature);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vcn) failed.\n");
return false;
if (info->ip[AMD_IP_VCN_DEC].num_queues || info->ip[AMD_IP_VCN_UNIFIED].num_queues) {
r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_VCN, 0, 0, &vidip_fw_version, &vidip_fw_feature);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vcn) failed.\n");
return false;
} else {
info->vcn_dec_version = (vidip_fw_version & 0x0F000000) >> 24;
info->vcn_enc_major_version = (vidip_fw_version & 0x00F00000) >> 20;
info->vcn_enc_minor_version = (vidip_fw_version & 0x000FF000) >> 12;
}
} else if (info->ip[AMD_IP_VCE].num_queues) {
r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_VCE, 0, 0, &vidip_fw_version, &vidip_fw_feature);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
return false;
} else
info->vce_fw_version = vidip_fw_version;
} else if (info->ip[AMD_IP_UVD].num_queues) {
r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_UVD, 0, 0, &vidip_fw_version, &vidip_fw_feature);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
return false;
} else
info->uvd_fw_version = vidip_fw_version;
}
r = amdgpu_query_sw_info(dev, amdgpu_sw_info_address32_hi, &info->address32_hi);
@ -1029,11 +1046,6 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->max_se = device_info.num_shader_engines;
info->max_sa_per_se = device_info.num_shader_arrays_per_engine;
info->num_cu_per_sh = device_info.num_cu_per_sh;
info->uvd_fw_version = info->ip[AMD_IP_UVD].num_queues ? uvd_version : 0;
info->vce_fw_version = info->ip[AMD_IP_VCE].num_queues ? vce_version : 0;
info->vcn_dec_version = (vcn_version & 0x0F000000) >> 24;
info->vcn_enc_major_version = (vcn_version & 0x00F00000) >> 20;
info->vcn_enc_minor_version = (vcn_version & 0x000FF000) >> 12;
info->memory_freq_mhz_effective *= ac_memory_ops_per_clock(info->vram_type);
@ -1842,19 +1854,59 @@ void ac_print_gpu_info(const struct radeon_info *info, FILE *f)
fprintf(f, " pfp_fw_feature = %i\n", info->pfp_fw_feature);
fprintf(f, "Multimedia info:\n");
fprintf(f, " vce_encode = %u\n", info->ip[AMD_IP_VCE].num_queues);
if (info->ip[AMD_IP_VCN_DEC].num_queues || info->ip[AMD_IP_VCN_UNIFIED].num_queues) {
if (info->family >= CHIP_NAVI31 || info->family == CHIP_GFX940)
fprintf(f, " vcn_unified = %u\n", info->ip[AMD_IP_VCN_UNIFIED].num_instances);
else {
fprintf(f, " vcn_decode = %u\n", info->ip[AMD_IP_VCN_DEC].num_instances);
fprintf(f, " vcn_encode = %u\n", info->ip[AMD_IP_VCN_ENC].num_instances);
}
fprintf(f, " vcn_enc_major_version = %u\n", info->vcn_enc_major_version);
fprintf(f, " vcn_enc_minor_version = %u\n", info->vcn_enc_minor_version);
fprintf(f, " vcn_dec_version = %u\n", info->vcn_dec_version);
} else if (info->ip[AMD_IP_VCE].num_queues) {
fprintf(f, " vce_encode = %u\n", info->ip[AMD_IP_VCE].num_queues);
fprintf(f, " vce_fw_version = %u\n", info->vce_fw_version);
fprintf(f, " vce_harvest_config = %i\n", info->vce_harvest_config);
} else if (info->ip[AMD_IP_UVD].num_queues)
fprintf(f, " uvd_fw_version = %u\n", info->uvd_fw_version);
if (info->family >= CHIP_NAVI31 || info->family == CHIP_GFX940)
fprintf(f, " vcn_unified = %u\n", info->ip[AMD_IP_VCN_UNIFIED].num_queues);
else {
fprintf(f, " vcn_decode = %u\n", info->ip[AMD_IP_VCN_DEC].num_queues);
fprintf(f, " vcn_encode = %u\n", info->ip[AMD_IP_VCN_ENC].num_queues);
if (info->ip[AMD_IP_VCN_JPEG].num_queues)
fprintf(f, " jpeg_decode = %u\n", info->ip[AMD_IP_VCN_JPEG].num_instances);
if ((info->drm_minor >= 41) &&
(info->ip[AMD_IP_VCN_DEC].num_queues || info->ip[AMD_IP_VCN_UNIFIED].num_queues
|| info->ip[AMD_IP_VCE].num_queues || info->ip[AMD_IP_UVD].num_queues)) {
char max_res_dec[64] = {0}, max_res_enc[64] = {0};
char codec_str[][8] = {
[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2] = "mpeg2",
[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4] = "mpeg4",
[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1] = "vc1",
[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC] = "h264",
[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC] = "hevc",
[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG] = "jpeg",
[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9] = "vp9",
[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1] = "av1",
};
fprintf(f, " %-8s %-4s %-16s %-4s %-16s\n",
"codec", "dec", "max_resolution", "enc", "max_resolution");
for (unsigned i = 0; i < AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT; i++) {
if (info->dec_caps.codec_info[i].valid)
sprintf(max_res_dec, "%ux%u", info->dec_caps.codec_info[i].max_width,
info->dec_caps.codec_info[i].max_height);
else
sprintf(max_res_dec, "%s", "-");
if (info->enc_caps.codec_info[i].valid)
sprintf(max_res_enc, "%ux%u", info->enc_caps.codec_info[i].max_width,
info->enc_caps.codec_info[i].max_height);
else
sprintf(max_res_enc, "%s", "-");
fprintf(f, " %-8s %-4s %-16s %-4s %-16s\n", codec_str[i],
info->dec_caps.codec_info[i].valid ? "*" : "-", max_res_dec,
info->enc_caps.codec_info[i].valid ? "*" : "-", max_res_enc);
}
}
fprintf(f, " uvd_fw_version = %u\n", info->uvd_fw_version);
fprintf(f, " vce_fw_version = %u\n", info->vce_fw_version);
fprintf(f, " vce_harvest_config = %i\n", info->vce_harvest_config);
fprintf(f, "Kernel & winsys capabilities:\n");
fprintf(f, " drm = %i.%i.%i\n", info->drm_major, info->drm_minor, info->drm_patchlevel);
fprintf(f, " has_userptr = %i\n", info->has_userptr);