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r600: Emit EOP for more CF instruction types
So far on pre-cayman chipsets the CF instructions CF_OP_LOOP_END,
CF_OP_CALL_FS, CF_OP_POP, and CF_OP_GDS an extra CF_NOP instruction
was added to add the EOP flag, even though this is not actually
needed, because all these instrutions support the EOP flag.
This patch removes the fixup code, adds setting the EOP flag for the
according instructions as well as others like CF_OP_TEX and CF_OP_VTX,
and adds writing out EOP for this type of instruction in the disassembler.
This also fixes a bug where shaders were created that didn't actually have
the EOP flag set in the last CF instruction, which might have resulted
in GPU lockups.
[airlied: cleaned up a little]
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 1d076aafbc)
This commit is contained in:
parent
a8a5a97f46
commit
c2ff8e3e5d
4 changed files with 16 additions and 7 deletions
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@ -71,9 +71,12 @@ int eg_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
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} else if (cfop->flags & CF_CLAUSE) {
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/* CF_TEX/VTX (CF_ALU already handled above) */
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bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
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bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(opcode) |
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bc->bytecode[id] = S_SQ_CF_WORD1_CF_INST(opcode) |
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S_SQ_CF_WORD1_BARRIER(1) |
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S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
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if (bc->chip_class == EVERGREEN) /* no EOP on cayman */
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bc->bytecode[id] |= S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program);
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id++;
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} else if (cfop->flags & CF_EXP) {
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/* EXPORT instructions */
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bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
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@ -111,12 +114,14 @@ int eg_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
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} else {
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/* other instructions */
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bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
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bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(opcode)|
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bc->bytecode[id] = S_SQ_CF_WORD1_CF_INST(opcode) |
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S_SQ_CF_WORD1_BARRIER(1) |
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S_SQ_CF_WORD1_COND(cf->cond) |
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S_SQ_CF_WORD1_POP_COUNT(cf->pop_count) |
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S_SQ_CF_WORD1_COUNT(cf->count) |
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S_SQ_CF_WORD1_END_OF_PROGRAM(cf->end_of_program);
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S_SQ_CF_WORD1_COUNT(cf->count);
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if (bc->chip_class == EVERGREEN) /* no EOP on cayman */
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bc->bytecode[id] |= S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program);
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id++;
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}
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}
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return 0;
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@ -1629,7 +1629,8 @@ static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_byt
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*bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
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*bytecode++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R600, cf->op)) |
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S_SQ_CF_WORD1_BARRIER(1) |
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S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
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S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1)|
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S_SQ_CF_WORD1_END_OF_PROGRAM(cf->end_of_program);
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}
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/* common for r600/r700 - eg in eg_asm.c */
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@ -2092,6 +2093,8 @@ void r600_bytecode_disasm(struct r600_bytecode *bc)
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bc->bytecode[id + 1], cfop->name);
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fprintf(stderr, "%d @%d ", cf->ndw / 4, cf->addr);
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fprintf(stderr, "\n");
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if (cf->end_of_program)
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fprintf(stderr, "EOP ");
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} else if (cfop->flags & CF_EXP) {
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int o = 0;
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const char *exp_type[] = {"PIXEL", "POS ", "PARAM"};
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@ -3658,7 +3658,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
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last = r600_isa_cf(ctx.bc->cf_last->op);
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/* alu clause instructions don't have EOP bit, so add NOP */
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if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_CALL_FS || ctx.bc->cf_last->op == CF_OP_POP || ctx.bc->cf_last->op == CF_OP_GDS)
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if (!last || last->flags & CF_ALU)
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r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
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ctx.bc->cf_last->end_of_program = 1;
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@ -30,7 +30,8 @@ void r700_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_c
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*bytecode++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R700, cf->op)) |
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S_SQ_CF_WORD1_BARRIER(1) |
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S_SQ_CF_WORD1_COUNT(count) |
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S_SQ_CF_WORD1_COUNT_3(count >> 3);
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S_SQ_CF_WORD1_COUNT_3(count >> 3)|
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S_SQ_CF_WORD1_END_OF_PROGRAM(cf->end_of_program);
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}
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int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
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