diff --git a/src/freedreno/.gitlab-ci/reference/crash.log b/src/freedreno/.gitlab-ci/reference/crash.log
index fe1ef58c0a9..bf9eba41180 100644
--- a/src/freedreno/.gitlab-ci/reference/crash.log
+++ b/src/freedreno/.gitlab-ci/reference/crash.log
@@ -634,8 +634,8 @@ registers:
 	00000000	CP_PROTECT_STATUS: 0
 	00000707	0x826: 00000707
 	00000001	0x827: 00000001
-	00009000	CP_SQE_INSTR_BASE_LO: 0x9000
-	00010000	CP_SQE_INSTR_BASE_HI: 0x10000
+	00009000	CP_SQE_INSTR_BASE: 0x9000
+	00010000	CP_SQE_INSTR_BASE+0x1: 0x10000
 	00000000	0x832: 00000000
 	00000000	0x833: 00000000
 	00000000	CP_MISC_CNTL: 0
@@ -1125,16 +1125,16 @@ registers:
 	00180000	PC_DBG_ECO_CNTL: 0x180000
 	00000001	PC_ADDR_MODE_CNTL: ADDR_64B
 	00000000	0x9e03: 00000000
-	00000000	0x9e04: 00000000
-	00000000	0x9e05: 00000000
-	00000000	0x9e06: 00000000
-	00000000	0x9e07: 00000000
+	00000000	PC_DRAW_INDX_BASE: 0
+	00000000	PC_DRAW_INDX_BASE+0x1: 0
+	00000000	PC_DRAW_FIRST_INDX: 0
+	00000000	PC_DRAW_MAX_INDICES: 0
 	00000000	PC_TESSFACTOR_ADDR: 0
 	00000000	PC_TESSFACTOR_ADDR_HI: 0
 	00000001	0x9e0a: 00000001
-	00004080	0x9e0b: 00004080
-	00000000	0x9e0c: 00000000
-	00000003	0x9e0d: 00000003
+	00004080	PC_DRAW_INITIATOR: { PRIM_TYPE = DI_PT_NONE | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_8_BIT | PATCH_TYPE = TESS_QUADS | 0x4000 }
+	00000000	PC_DRAW_NUM_INSTANCES: 0
+	00000003	PC_DRAW_NUM_INDICES: 3
 	00000000	0x9e0e: 00000000
 	00010000	PC_VSTREAM_CONTROL: { VSC_SIZE = 1 | VSC_N = 0 }
 	00000000	PC_BIN_PRIM_STRM: 0
@@ -1143,7 +1143,7 @@ registers:
 	00000000	PC_BIN_DRAW_STRM_HI: 0
 	00000000	0x9e16: 00000000
 	00000000	0x9e19: 00000000
-	00000000	0x9e1c: 00000000
+	00000000	PC_VISIBILITY_OVERRIDE: { 0 }
 	00000000	0x9e20: 00000000
 	00000000	0x9e21: 00000000
 	00000000	0x9e22: 00000000
@@ -2993,7 +2993,7 @@ indexed-registers:
 	00000000	0x127: 00000000
 	00000000	0x128: 00000000
 	00000000	0x129: 00000000
-	00000101	0x12a: 00000101
+	00000101	MARKER: 0x101
 	00000004	MODE_BITMASK: 0x4
 	00000000	0x12c: 00000000
 	00000000	0x12d: 00000000
diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index 43eb469adda..67e78bd0ae2 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -978,8 +978,7 @@ to upconvert to 32b float internally?
 	<reg32 offset="0x0821" name="CP_HW_FAULT"/>
 	<reg32 offset="0x0823" name="CP_INTERRUPT_STATUS"/>
 	<reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>
-	<reg32 offset="0x0830" name="CP_SQE_INSTR_BASE_LO"/>
-	<reg32 offset="0x0831" name="CP_SQE_INSTR_BASE_HI"/>
+	<reg64 offset="0x0830" name="CP_SQE_INSTR_BASE"/>
 	<reg32 offset="0x0840" name="CP_MISC_CNTL"/>
 	<reg32 offset="0x0844" name="CP_APRIV_CNTL"/>
 	<!-- all the threshold values seem to be in units of quad-dwords: -->
@@ -1095,6 +1094,7 @@ to upconvert to 32b float internally?
 	<reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST"/>
 	<reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD"/>
 	<reg32 offset="0x0B34" name="CP_LPAC_PROG_FIFO_SIZE"/>
+	<reg64 offset="0x0b82" name="CP_LPAC_SQE_INSTR_BASE"/>
 	<reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
 	<reg32 offset="0x0201" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK"/>
 	<reg32 offset="0x0210" name="RBBM_STATUS">
@@ -2492,6 +2492,13 @@ to upconvert to 32b float internally?
 		<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
 	</reg32>
 
+	<!--
+		0x9880 written in a lot of places by SQE, same value gets written
+		to control reg 0x12a.  Set by CP_SET_MARKER, so lets name it after
+		that
+	 -->
+	<reg32 offset="0x9880" name="PC_MARKER"/>
+
 	<!-- 0x9843-0x997f invalid -->
 
 	<reg32 offset="0x9981" name="PC_POLYGON_MODE">
@@ -2580,8 +2587,20 @@ to upconvert to 32b float internally?
 	<!-- TODO: 0x9e00-0xa000 range incomplete -->
 	<reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL"/>
 	<reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
+	<reg64 offset="0x9e04" name="PC_DRAW_INDX_BASE"/>
+	<reg32 offset="0x9e06" name="PC_DRAW_FIRST_INDX" type="uint"/>
+	<reg32 offset="0x9e07" name="PC_DRAW_MAX_INDICES" type="uint"/>
 	<reg64 offset="0x9e08" name="PC_TESSFACTOR_ADDR" type="waddress" align="32"/>
 
+	<reg32 offset="0x9e0b" name="PC_DRAW_INITIATOR" type="vgt_draw_initiator_a4xx">
+		<doc>
+			Possibly not really "initiating" the draw but the layout is similar
+			to VGT_DRAW_INITIATOR on older gens
+		</doc>
+	</reg32>
+	<reg32 offset="0x9e0c" name="PC_DRAW_NUM_INSTANCES" type="uint"/>
+	<reg32 offset="0x9e0d" name="PC_DRAW_NUM_INDICES" type="uint"/>
+
 	<!-- These match the contents of CP_SET_BIN_DATA (not written directly) -->
 	<reg32 offset="0x9e11" name="PC_VSTREAM_CONTROL">
 		<bitfield name="UNK0" low="0" high="15"/>
@@ -2591,6 +2610,11 @@ to upconvert to 32b float internally?
 	<reg64 offset="0x9e12" name="PC_BIN_PRIM_STRM" type="waddress" align="32"/>
 	<reg64 offset="0x9e14" name="PC_BIN_DRAW_STRM" type="waddress" align="32"/>
 
+	<reg32 offset="0x9e1c" name="PC_VISIBILITY_OVERRIDE">
+		<doc>Written by CP_SET_VISIBILITY_OVERRIDE handler</doc>
+		<bitfield name="OVERRIDE" pos="0" type="boolean"/>
+	</reg32>
+
 	<array offset="0x9e34" name="PC_PERFCTR_PC_SEL" stride="1" length="8"/>
 
 	<!-- always 0x0 -->
diff --git a/src/freedreno/registers/adreno/adreno_control_regs.xml b/src/freedreno/registers/adreno/adreno_control_regs.xml
index ed7c86b7700..24ce699c69f 100644
--- a/src/freedreno/registers/adreno/adreno_control_regs.xml
+++ b/src/freedreno/registers/adreno/adreno_control_regs.xml
@@ -43,6 +43,17 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<doc>
 		Writing to this triggers a register write and auto-increments
 		REG_WRITE_ADDR.
+
+		Note that there seems to be some upper bits that are possilby
+		flags, ie:
+
+		 l284:  0d12: 8a8c0003  mov $0c, 0x0003 &lt;&lt; 20
+		              GPR:  $0c: 00300000
+		        0d13: 318c9e0b  or $0c, $0c, 0x9e0b
+		              GPR:  $0c: 00309e0b
+		        0d14: a80c0024  cwrite $0c, [$00 + @REG_WRITE_ADDR], 0x0
+		              CTRL: @REG_WRITE_ADDR: 00309e0b
+
 	</doc>
 	<reg32 name="REG_WRITE" offset="0x025"/>
 
@@ -62,7 +73,38 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<reg32 name="QUERY_PEND_CTR" offset="0x039"/>
 	<reg32 name="CACHE_FLUSH_PEND_CTR" offset="0x03a"/>
 
-	<reg32 name="DRAW_STATE_SEL" offset="0x041"/>
+	<reg32 name="DRAW_STATE_SEL" offset="0x041">
+		<doc>
+			SQE writes DRAW_STATE_SEL to select the SDS state group, and
+			then reads out the SDS header (DRAW_STATE_HDR), ie. the first
+			dword in the state group entry (see CP_SET_DRAW_STATE), and
+			base address of the state group cmdstream (DRAW_STATE_BASE)
+		</doc>
+	</reg32>
+	<reg64 name="SDS_BASE" offset="0x042">
+		<doc>
+			base address for executing draw state group when IB_LEVEL
+			is set to 3 (ie. it's a bit like IB3 equiv of IBn_BASE)
+
+			Note that SDS_BASE/SDS_DWORDS seem to be per-state-group,
+			the values reflected switch when DRAW_STATE_SEL is written.
+		</doc>
+	</reg64>
+	<reg32 name="SDS_DWORDS" offset="0x044">
+		<doc>
+			state group equiv of IBn_DWORDS
+		</doc>
+	</reg32>
+
+	<reg64 name="DRAW_STATE_BASE" offset="0x045"/>
+	<reg32 name="DRAW_STATE_HDR" offset="0x047">
+		<doc>
+			Contains information from the first dword of the state group
+			entry in CP_SET_DRAW_STATE, but format isn't exactly the
+			same.  The # of dwords is in low 16b, and mode mask is in
+			high 16 bits
+		</doc>
+	</reg32>
 	<reg32 name="DRAW_STATE_ACTIVE_BITMASK" offset="0x049"/>
 	<reg32 name="DRAW_STATE_SET" offset="0x04a"/>
 
@@ -112,6 +154,11 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 
 	<reg32 name="PREEMPTION_INFO" offset="0x126"/>
 
+	<doc>
+		Seems to be a shadow for PC_MARKER
+	</doc>
+	<reg32 name="MARKER" offset="0x12a"/>
+
 	<doc>
 		Set by SET_MARKER, used to conditionally execute
 		CP_COND_REG_EXEC and draw states.