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anv: Put a VkPipelineShaderStageCreateInfo* in anv_pipeline_stage
It's an entirely temporary struct used by the compile process and never escapes vkCreate*Pipelines so it's safe to just stuff the pointer in there. This makes it easier to use some of our new helpers. Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17337>
This commit is contained in:
Jason Ekstrand
Marge Bot
parent
56b815e91d
commit
c2b3d9ca2b
1 changed files with 27 additions and 32 deletions
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@ -546,9 +546,7 @@ populate_bs_prog_key(const struct anv_device *device,
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struct anv_pipeline_stage {
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gl_shader_stage stage;
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const struct vk_shader_module *module;
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const char *entrypoint;
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const VkSpecializationInfo *spec_info;
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const VkPipelineShaderStageCreateInfo *info;
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unsigned char shader_sha1[20];
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@ -597,7 +595,7 @@ anv_pipeline_hash_graphics(struct anv_graphics_pipeline *pipeline,
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_mesa_sha1_update(&ctx, &rba, sizeof(rba));
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for (unsigned s = 0; s < ARRAY_SIZE(pipeline->shaders); s++) {
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if (stages[s].entrypoint) {
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if (stages[s].info) {
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_mesa_sha1_update(&ctx, stages[s].shader_sha1,
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sizeof(stages[s].shader_sha1));
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_mesa_sha1_update(&ctx, &stages[s].key, brw_prog_key_size(s));
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@ -700,12 +698,13 @@ anv_pipeline_stage_get_nir(struct anv_pipeline *pipeline,
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return nir;
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}
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VK_FROM_HANDLE(vk_shader_module, module, stage->info->module);
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nir = anv_shader_compile_to_nir(pipeline->device,
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mem_ctx,
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stage->module,
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stage->entrypoint,
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module,
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stage->info->pName,
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stage->stage,
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stage->spec_info);
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stage->info->pSpecializationInfo);
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if (nir) {
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anv_device_upload_nir(pipeline->device, cache, nir, stage->shader_sha1);
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return nir;
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@ -1413,14 +1412,13 @@ anv_pipeline_compile_graphics(struct anv_graphics_pipeline *pipeline,
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VkResult result;
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for (uint32_t i = 0; i < info->stageCount; i++) {
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const VkPipelineShaderStageCreateInfo *sinfo = &info->pStages[i];
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VK_FROM_HANDLE(vk_shader_module, module, sinfo->module);
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gl_shader_stage stage = vk_to_mesa_shader_stage(sinfo->stage);
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int64_t stage_start = os_time_get_nano();
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stages[stage].stage = stage;
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stages[stage].module = vk_shader_module_from_handle(sinfo->module);
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stages[stage].entrypoint = sinfo->pName;
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stages[stage].spec_info = sinfo->pSpecializationInfo;
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stages[stage].info = sinfo;
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vk_pipeline_hash_shader_stage(&info->pStages[i], stages[stage].shader_sha1);
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const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *rss_info =
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@ -1428,7 +1426,7 @@ anv_pipeline_compile_graphics(struct anv_graphics_pipeline *pipeline,
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PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT);
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enum brw_subgroup_size_type subgroup_size_type =
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anv_subgroup_size_type(stage, stages[stage].module, sinfo->flags, rss_info);
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anv_subgroup_size_type(stage, module, sinfo->flags, rss_info);
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const struct anv_device *device = pipeline->base.device;
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switch (stage) {
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@ -1493,7 +1491,7 @@ anv_pipeline_compile_graphics(struct anv_graphics_pipeline *pipeline,
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anv_pipeline_hash_graphics(pipeline, layout, stages, sha1);
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for (unsigned s = 0; s < ARRAY_SIZE(pipeline->shaders); s++) {
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if (!stages[s].entrypoint)
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if (!stages[s].info)
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continue;
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stages[s].cache_key.stage = s;
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@ -1507,7 +1505,7 @@ anv_pipeline_compile_graphics(struct anv_graphics_pipeline *pipeline,
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unsigned found = 0;
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unsigned cache_hits = 0;
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for (unsigned s = 0; s < ARRAY_SIZE(pipeline->shaders); s++) {
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if (!stages[s].entrypoint)
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if (!stages[s].info)
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continue;
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int64_t stage_start = os_time_get_nano();
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@ -1537,7 +1535,7 @@ anv_pipeline_compile_graphics(struct anv_graphics_pipeline *pipeline,
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}
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/* We found all our shaders in the cache. We're done. */
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for (unsigned s = 0; s < ARRAY_SIZE(pipeline->shaders); s++) {
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if (!stages[s].entrypoint)
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if (!stages[s].info)
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continue;
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anv_pipeline_add_executables(&pipeline->base, &stages[s],
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@ -1591,7 +1589,7 @@ anv_pipeline_compile_graphics(struct anv_graphics_pipeline *pipeline,
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for (unsigned i = 0; i < ARRAY_SIZE(shader_order); i++) {
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gl_shader_stage s = shader_order[i];
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if (!stages[s].entrypoint)
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if (!stages[s].info)
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continue;
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int64_t stage_start = os_time_get_nano();
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@ -1637,7 +1635,7 @@ anv_pipeline_compile_graphics(struct anv_graphics_pipeline *pipeline,
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struct anv_pipeline_stage *next_stage = NULL;
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for (int i = ARRAY_SIZE(shader_order) - 1; i >= 0; i--) {
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gl_shader_stage s = shader_order[i];
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if (!stages[s].entrypoint)
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if (!stages[s].info)
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continue;
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switch (s) {
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@ -1689,7 +1687,7 @@ anv_pipeline_compile_graphics(struct anv_graphics_pipeline *pipeline,
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struct anv_pipeline_stage *prev_stage = NULL;
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for (unsigned i = 0; i < ARRAY_SIZE(shader_order); i++) {
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gl_shader_stage s = shader_order[i];
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if (!stages[s].entrypoint)
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if (!stages[s].info)
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continue;
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int64_t stage_start = os_time_get_nano();
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@ -1724,15 +1722,15 @@ anv_pipeline_compile_graphics(struct anv_graphics_pipeline *pipeline,
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*/
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const struct intel_device_info *devinfo = &pipeline->base.device->info;
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if (devinfo->has_coarse_pixel_primitive_and_cb &&
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stages[MESA_SHADER_FRAGMENT].entrypoint &&
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stages[MESA_SHADER_FRAGMENT].info &&
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stages[MESA_SHADER_FRAGMENT].key.wm.coarse_pixel &&
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stages[MESA_SHADER_MESH].entrypoint == NULL) {
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stages[MESA_SHADER_MESH].info == NULL) {
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struct anv_pipeline_stage *last_psr = NULL;
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for (unsigned i = 0; i < ARRAY_SIZE(shader_order); i++) {
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gl_shader_stage s = shader_order[ARRAY_SIZE(shader_order) - i - 1];
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if (!stages[s].entrypoint ||
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if (!stages[s].info ||
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!gl_shader_stage_can_set_fragment_shading_rate(s))
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continue;
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@ -1747,7 +1745,7 @@ anv_pipeline_compile_graphics(struct anv_graphics_pipeline *pipeline,
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prev_stage = NULL;
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for (unsigned i = 0; i < ARRAY_SIZE(shader_order); i++) {
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gl_shader_stage s = shader_order[i];
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if (!stages[s].entrypoint)
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if (!stages[s].info)
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continue;
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int64_t stage_start = os_time_get_nano();
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@ -1872,9 +1870,7 @@ anv_pipeline_compile_cs(struct anv_compute_pipeline *pipeline,
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struct anv_pipeline_stage stage = {
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.stage = MESA_SHADER_COMPUTE,
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.module = module,
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.entrypoint = sinfo->pName,
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.spec_info = sinfo->pSpecializationInfo,
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.info = &info->stage,
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.cache_key = {
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.stage = MESA_SHADER_COMPUTE,
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},
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@ -1891,7 +1887,7 @@ anv_pipeline_compile_cs(struct anv_compute_pipeline *pipeline,
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PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO);
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const enum brw_subgroup_size_type subgroup_size_type =
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anv_subgroup_size_type(MESA_SHADER_COMPUTE, stage.module, info->stage.flags, rss_info);
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anv_subgroup_size_type(MESA_SHADER_COMPUTE, module, info->stage.flags, rss_info);
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populate_cs_prog_key(device, subgroup_size_type,
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device->robust_buffer_access,
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@ -2689,16 +2685,15 @@ anv_pipeline_init_ray_tracing_stages(struct anv_ray_tracing_pipeline *pipeline,
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for (uint32_t i = 0; i < info->stageCount; i++) {
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const VkPipelineShaderStageCreateInfo *sinfo = &info->pStages[i];
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if (sinfo->module == VK_NULL_HANDLE)
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VK_FROM_HANDLE(vk_shader_module, module, sinfo->module);
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if (module != NULL)
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continue;
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int64_t stage_start = os_time_get_nano();
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stages[i] = (struct anv_pipeline_stage) {
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.stage = vk_to_mesa_shader_stage(sinfo->stage),
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.module = vk_shader_module_from_handle(sinfo->module),
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.entrypoint = sinfo->pName,
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.spec_info = sinfo->pSpecializationInfo,
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.info = sinfo,
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.cache_key = {
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.stage = vk_to_mesa_shader_stage(sinfo->stage),
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},
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@ -2761,7 +2756,7 @@ anv_pipeline_load_cached_shaders(struct anv_ray_tracing_pipeline *pipeline,
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{
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uint32_t shaders = 0, cache_hits = 0;
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for (uint32_t i = 0; i < info->stageCount; i++) {
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if (stages[i].entrypoint == NULL)
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if (stages[i].info == NULL)
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continue;
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shaders++;
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@ -2833,7 +2828,7 @@ anv_pipeline_compile_ray_tracing(struct anv_ray_tracing_pipeline *pipeline,
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}
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for (uint32_t i = 0; i < info->stageCount; i++) {
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if (stages[i].entrypoint == NULL)
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if (stages[i].info == NULL)
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continue;
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int64_t stage_start = os_time_get_nano();
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@ -2851,7 +2846,7 @@ anv_pipeline_compile_ray_tracing(struct anv_ray_tracing_pipeline *pipeline,
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}
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for (uint32_t i = 0; i < info->stageCount; i++) {
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if (stages[i].entrypoint == NULL)
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if (stages[i].info == NULL)
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continue;
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/* Shader found in cache already. */
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