From c2932690c6366a58922daea9b75e2b27d30dce2e Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 20 Jan 2021 17:29:14 +0100 Subject: [PATCH] radv: fix a sync issue with geometry shader primitives query on GFX10+ When NGG is used, the hw can't know the number of geometry shader primitives. To fix that, the NGG geometry shader accumulates itself the number of primitives by using an atomic operation directly to GDS. Then, begin/query copy the start/stop values from GDS to the query pool buffer using a PS_DONE event. This was actually wrong because PS_DONE is completely asynchronous to everything and executed when the preceding draws finish pixel shaders. Fix this by using a COPY_DATA packet which is synced with CP. This fixes random failures on Sienna Cichlid with dEQP-VK.query_pool.statistics_query.*.geometry_shader_primitives.*. Cc: Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: (cherry picked from commit 085e2ce3d49c36ad2c119313e47c0ac685828a61) --- .pick_status.json | 2 +- src/amd/vulkan/radv_query.c | 30 ++++++++++++++++-------------- 2 files changed, 17 insertions(+), 15 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 422282faffc..e3c03daf0f9 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -1057,7 +1057,7 @@ "description": "radv: fix a sync issue with geometry shader primitives query on GFX10+", "nominated": true, "nomination_type": 0, - "resolution": 0, + "resolution": 1, "master_sha": null, "because_sha": null }, diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c index d49bc0f0564..90512d4f276 100644 --- a/src/amd/vulkan/radv_query.c +++ b/src/amd/vulkan/radv_query.c @@ -1679,13 +1679,14 @@ static void emit_begin_query(struct radv_cmd_buffer *cmd_buffer, va += 8 * idx; - si_cs_emit_write_event_eop(cs, - cmd_buffer->device->physical_device->rad_info.chip_class, - radv_cmd_buffer_uses_mec(cmd_buffer), - V_028A90_PS_DONE, 0, - EOP_DST_SEL_TC_L2, - EOP_DATA_SEL_GDS, - va, EOP_DATA_GDS(0, 1), 0); + radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); + radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_GDS) | + COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) | + COPY_DATA_WR_CONFIRM); + radeon_emit(cs, 0); + radeon_emit(cs, 0); + radeon_emit(cs, va); + radeon_emit(cs, va >> 32); /* Record that the command buffer needs GDS. */ cmd_buffer->gds_needed = true; @@ -1769,13 +1770,14 @@ static void emit_end_query(struct radv_cmd_buffer *cmd_buffer, va += 8 * idx; - si_cs_emit_write_event_eop(cs, - cmd_buffer->device->physical_device->rad_info.chip_class, - radv_cmd_buffer_uses_mec(cmd_buffer), - V_028A90_PS_DONE, 0, - EOP_DST_SEL_TC_L2, - EOP_DATA_SEL_GDS, - va, EOP_DATA_GDS(0, 1), 0); + radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); + radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_GDS) | + COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) | + COPY_DATA_WR_CONFIRM); + radeon_emit(cs, 0); + radeon_emit(cs, 0); + radeon_emit(cs, va); + radeon_emit(cs, va >> 32); cmd_buffer->state.active_pipeline_gds_queries--; }