mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-08 09:08:10 +02:00
nak: Implement more attribute I/O
This commits implement load/store_per_vertex* and load_output which are required for tessellation shaders. Because things are getting a bit complicated, it's easier to combine all the attribute load/store ops in a single case in the match. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24998>
This commit is contained in:
Faith Ekstrand
Marge Bot
parent
091410c708
commit
c2768736c9
2 changed files with 149 additions and 115 deletions
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@ -16,7 +16,7 @@ use crate::util::DivCeil;
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use nak_bindings::*;
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use std::cmp::min;
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use std::cmp::{max, min};
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use std::collections::{HashMap, HashSet};
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fn init_info_from_nir(nir: &nir_shader, sm: u8) -> ShaderInfo {
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@ -61,7 +61,11 @@ fn init_info_from_nir(nir: &nir_shader, sm: u8) -> ShaderInfo {
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})
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}
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MESA_SHADER_TESS_CTRL => {
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ShaderStageInfo::TessellationInit(Default::default())
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let info_tess = unsafe { &nir.info.__bindgen_anon_1.tess };
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ShaderStageInfo::TessellationInit(TessellationInitShaderInfo {
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per_patch_attribute_count: 6,
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threads_per_patch: info_tess.tcs_vertices_out,
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})
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}
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MESA_SHADER_TESS_EVAL => ShaderStageInfo::Tessellation,
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_ => panic!("Unknown shader stage"),
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@ -91,7 +95,7 @@ fn init_info_from_nir(nir: &nir_shader, sm: u8) -> ShaderInfo {
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attr_out: [0; 4],
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// TODO: figure out how to fill this.
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store_req_start: 0xff,
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store_req_start: u8::MAX,
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store_req_end: 0,
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}),
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_ => panic!("Unknown shader stage"),
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@ -1362,22 +1366,85 @@ impl<'a> ShaderFromNir<'a> {
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});
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self.set_dst(&intrin.def, dst);
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}
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nir_intrinsic_load_input | nir_intrinsic_load_per_vertex_input => {
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assert!(intrin.def.bit_size() == 32);
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let comps = intrin.def.num_components();
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let dst = b.alloc_ssa(RegFile::GPR, comps);
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nir_intrinsic_load_input
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| nir_intrinsic_load_output
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| nir_intrinsic_load_per_vertex_input
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| nir_intrinsic_load_per_vertex_output
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| nir_intrinsic_store_output
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| nir_intrinsic_store_per_vertex_output => {
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let comps = intrin.num_components;
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let store_data = match intrin.intrinsic {
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nir_intrinsic_load_input
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| nir_intrinsic_load_output
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| nir_intrinsic_load_per_vertex_input
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| nir_intrinsic_load_per_vertex_output => {
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assert!(intrin.def.bit_size() == 32);
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assert!(intrin.def.num_components() == comps);
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None
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}
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nir_intrinsic_store_output
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| nir_intrinsic_store_per_vertex_output => {
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assert!(srcs[0].bit_size() == 32);
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assert!(srcs[0].num_components() == comps);
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Some(self.get_src(&srcs[0]))
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}
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_ => panic!("Unhandled intrinsic"),
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};
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let (vtx, offset, offset_as_u32) = match intrin.intrinsic {
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nir_intrinsic_load_input => (
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nir_intrinsic_load_input | nir_intrinsic_load_output => (
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Src::new_zero(),
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self.get_src(&srcs[0]),
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srcs[0].as_uint(),
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),
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nir_intrinsic_load_per_vertex_input => (
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nir_intrinsic_load_per_vertex_input
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| nir_intrinsic_load_per_vertex_output => (
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self.get_src(&srcs[0]),
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self.get_src(&srcs[1]),
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srcs[1].as_uint(),
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),
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nir_intrinsic_store_output => (
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Src::new_zero(),
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self.get_src(&srcs[1]),
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srcs[1].as_uint(),
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),
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nir_intrinsic_store_per_vertex_output => (
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self.get_src(&srcs[1]),
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self.get_src(&srcs[2]),
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srcs[2].as_uint(),
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),
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_ => panic!("Unhandled intrinsic"),
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};
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let base = u16::try_from(intrin.base()).unwrap();
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let range = u16::try_from(intrin.range()).unwrap();
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let comp = u16::try_from(intrin.component()).unwrap();
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let (range, addr, offset) = match offset_as_u32 {
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Some(imm) => {
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let imm = u16::try_from(imm).unwrap();
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let addr = base + imm + 4 * comp;
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let range = addr..(addr + 4 * u16::from(comps));
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(range, addr, Src::new_zero())
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}
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None => {
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let range = base..(base + range);
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(range, base + 4 * comp, offset)
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}
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};
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let stage = self.nir.info.stage();
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let (output, patch) = match intrin.intrinsic {
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nir_intrinsic_load_input => {
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(false, stage == MESA_SHADER_TESS_EVAL)
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}
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nir_intrinsic_load_output | nir_intrinsic_store_output => {
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(true, stage == MESA_SHADER_TESS_CTRL)
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}
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nir_intrinsic_load_per_vertex_input => (false, false),
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nir_intrinsic_load_per_vertex_output
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| nir_intrinsic_store_per_vertex_output => (true, false),
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_ => panic!("Unhandled intrinsic"),
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};
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@ -1386,63 +1453,86 @@ impl<'a> ShaderFromNir<'a> {
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panic!("Stage does not support load_input")
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}
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ShaderIoInfo::Fragment(io) => {
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assert!(intrin.intrinsic == nir_intrinsic_load_input);
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let addr = u16::try_from(intrin.base()).unwrap()
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+ u16::try_from(offset_as_u32.unwrap()).unwrap()
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+ u16::try_from(intrin.component()).unwrap() * 4;
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if let Some(data) = store_data {
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// We assume these only ever happen in the
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// last block. This is ensured by
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// nir_lower_io_to_temporaries()
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assert!(offset_as_u32 == Some(0));
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assert!(addr % 4 == 0);
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let data = data.as_ssa().unwrap();
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for c in 0..usize::from(comps) {
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let idx =
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usize::from(addr / 4) + usize::from(c);
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self.fs_out_regs[idx] = data[c];
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}
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} else {
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let dst = b.alloc_ssa(RegFile::GPR, comps);
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for c in 0..comps {
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let c_addr = addr + 4 * u16::from(c);
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for c in 0..comps {
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let c_addr = addr + 4 * u16::from(c);
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io.mark_attr_read(c_addr, PixelImap::Constant);
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io.mark_attr_read(c_addr, PixelImap::Constant);
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b.push_op(OpIpa {
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dst: dst[usize::from(c)].into(),
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addr: c_addr,
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freq: InterpFreq::Constant,
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loc: InterpLoc::Default,
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offset: SrcRef::Zero.into(),
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});
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b.push_op(OpIpa {
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dst: dst[usize::from(c)].into(),
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addr: c_addr,
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freq: InterpFreq::Constant,
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loc: InterpLoc::Default,
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offset: SrcRef::Zero.into(),
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});
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}
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self.set_dst(&intrin.def, dst);
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}
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}
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ShaderIoInfo::Vtg(io) => {
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let base = u16::try_from(intrin.base()).unwrap();
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let range = u16::try_from(intrin.base()).unwrap();
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let comp = u16::try_from(intrin.component()).unwrap();
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let (addr, offset) = match offset_as_u32 {
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Some(imm) => {
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let imm = u16::try_from(imm).unwrap();
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let addr = base + imm + 4 * comp;
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io.mark_attrs_read(
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addr..(addr + 4 * u16::from(comps)),
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);
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(addr, Src::new_zero())
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if patch {
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match &mut self.info.stage {
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ShaderStageInfo::TessellationInit(stage) => {
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stage.per_patch_attribute_count = max(
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stage.per_patch_attribute_count,
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(range.end / 4).try_into().unwrap(),
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);
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}
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ShaderStageInfo::Tessellation => (),
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_ => panic!("Patch I/O not supported"),
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}
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None => {
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io.mark_attrs_read(base..(base + range));
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(base + 4 * comp, offset)
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} else {
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if output {
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if store_data.is_none() {
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io.mark_store_req(range.clone());
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}
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io.mark_attrs_written(range);
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} else {
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io.mark_attrs_read(range);
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}
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};
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}
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let access = AttrAccess {
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addr: addr,
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comps: comps,
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patch: false,
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output: false,
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patch: patch,
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output: output,
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flags: 0,
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};
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b.push_op(OpALd {
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dst: dst.into(),
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vtx: vtx,
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offset: offset,
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access: access,
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});
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if let Some(data) = store_data {
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b.push_op(OpASt {
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vtx: vtx,
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offset: offset,
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data: data,
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access: access,
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});
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} else {
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let dst = b.alloc_ssa(RegFile::GPR, comps);
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b.push_op(OpALd {
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dst: dst.into(),
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vtx: vtx,
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offset: offset,
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access: access,
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});
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self.set_dst(&intrin.def, dst);
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}
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}
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}
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self.set_dst(&intrin.def, dst);
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}
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nir_intrinsic_load_interpolated_input => {
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let bary =
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@ -1717,70 +1807,6 @@ impl<'a> ShaderFromNir<'a> {
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access: access,
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});
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}
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nir_intrinsic_store_output => {
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assert!(intrin.get_src(0).bit_size() == 32);
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let comps = intrin.num_components;
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let data = self.get_src(&srcs[0]);
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let vtx = Src::new_zero();
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let offset = self.get_src(&srcs[1]);
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let offset_as_u32 = srcs[1].as_uint();
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match &mut self.info.io {
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ShaderIoInfo::None => {
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panic!("Stage does not support load_input")
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}
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ShaderIoInfo::Fragment(io) => {
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/* We assume these only ever happen in the last block.
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* This is ensured by nir_lower_io_to_temporaries()
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*/
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let data = *self.get_src(&srcs[0]).as_ssa().unwrap();
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assert!(offset_as_u32 == Some(0));
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let base: u8 = intrin.base().try_into().unwrap();
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let comp: u8 = intrin.component().try_into().unwrap();
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assert!(base % 4 == 0);
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let out_idx = usize::from((base / 4) + comp);
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for c in 0..usize::from(comps) {
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self.fs_out_regs[out_idx + c] = data[c];
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}
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}
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ShaderIoInfo::Vtg(io) => {
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let base = u16::try_from(intrin.base()).unwrap();
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let range = u16::try_from(intrin.base()).unwrap();
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let comp = u16::try_from(intrin.component()).unwrap();
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let (addr, offset) = match offset_as_u32 {
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Some(imm) => {
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let imm = u16::try_from(imm).unwrap();
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let addr = base + imm + 4 * comp;
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io.mark_attrs_written(
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addr..(addr + 4 * u16::from(comps)),
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);
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(addr, Src::new_zero())
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}
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None => {
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io.mark_attrs_written(base..(base + range));
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(base + 4 * comp, offset)
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}
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};
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let access = AttrAccess {
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addr: addr,
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comps: comps,
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patch: false,
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output: true,
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flags: 0,
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};
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b.push_op(OpASt {
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vtx: vtx,
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offset: offset,
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data: data,
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access: access,
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});
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}
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}
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}
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nir_intrinsic_store_scratch => {
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let data = self.get_src(&srcs[0]);
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let size_B =
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@ -13,6 +13,7 @@ use crate::nak_cfg::CFG;
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use crate::nak_sph::{OutputTopology, PixelImap};
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use crate::{GetDebugFlags, DEBUG};
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use nak_ir_proc::*;
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use std::cmp::{max, min};
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use std::fmt;
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use std::iter::Zip;
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use std::ops::{BitAnd, BitOr, Deref, DerefMut, Index, IndexMut, Not, Range};
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@ -4735,7 +4736,7 @@ impl Default for GeometryShaderInfo {
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}
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}
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#[derive(Debug, Default)]
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#[derive(Debug)]
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pub struct TessellationInitShaderInfo {
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pub per_patch_attribute_count: u8,
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pub threads_per_patch: u8,
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@ -4804,6 +4805,13 @@ impl VtgIoInfo {
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pub fn mark_attrs_written(&mut self, addrs: Range<u16>) {
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self.mark_attrs(addrs, true);
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}
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pub fn mark_store_req(&mut self, addrs: Range<u16>) {
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let start = (addrs.start / 4).try_into().unwrap();
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let end = ((addrs.end - 1) / 4).try_into().unwrap();
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self.store_req_start = min(self.store_req_start, start);
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self.store_req_end = max(self.store_req_end, end);
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}
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}
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#[derive(Debug)]
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