diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c b/src/gallium/drivers/radeonsi/si_state_binning.c index f2485b15819..39a97ebd0ce 100644 --- a/src/gallium/drivers/radeonsi/si_state_binning.c +++ b/src/gallium/drivers/radeonsi/si_state_binning.c @@ -42,7 +42,7 @@ static struct uvec2 si_find_bin_size(struct si_screen *sscreen, const si_bin_siz return size; } -static struct uvec2 si_get_color_bin_size(struct si_context *sctx, unsigned cb_target_enabled_4bit) +static struct uvec2 gfx9_get_color_bin_size(struct si_context *sctx, unsigned cb_target_enabled_4bit) { unsigned num_fragments = sctx->framebuffer.nr_color_samples; unsigned sum = 0; @@ -156,7 +156,7 @@ static struct uvec2 si_get_color_bin_size(struct si_context *sctx, unsigned cb_t return si_find_bin_size(sctx->screen, table, sum); } -static struct uvec2 si_get_depth_bin_size(struct si_context *sctx) +static struct uvec2 gfx9_get_depth_bin_size(struct si_context *sctx) { struct si_state_dsa *dsa = sctx->queued.named.dsa; @@ -465,8 +465,8 @@ void si_emit_dpbb_state(struct si_context *sctx, unsigned index) if (sctx->gfx_level >= GFX10) { gfx10_get_bin_sizes(sctx, cb_target_enabled_4bit, &color_bin_size, &depth_bin_size); } else { - color_bin_size = si_get_color_bin_size(sctx, cb_target_enabled_4bit); - depth_bin_size = si_get_depth_bin_size(sctx); + color_bin_size = gfx9_get_color_bin_size(sctx, cb_target_enabled_4bit); + depth_bin_size = gfx9_get_depth_bin_size(sctx); } unsigned color_area = color_bin_size.x * color_bin_size.y; diff --git a/src/gallium/drivers/radeonsi/si_state_msaa.c b/src/gallium/drivers/radeonsi/si_state_msaa.c index fde56f8fb02..b69e4dbcbf3 100644 --- a/src/gallium/drivers/radeonsi/si_state_msaa.c +++ b/src/gallium/drivers/radeonsi/si_state_msaa.c @@ -142,10 +142,10 @@ static void si_get_sample_position(struct pipe_context *ctx, unsigned sample_cou out_value[1] = (GET_SY(sample_locs, sample_index) + 8) / 16.0f; } -static void si_emit_max_4_sample_locs(struct radeon_cmdbuf *cs, uint64_t centroid_priority, +static void si_emit_max_4_sample_locs(struct si_context *sctx, uint64_t centroid_priority, uint32_t sample_locs) { - radeon_begin(cs); + radeon_begin(&sctx->gfx_cs); radeon_set_context_reg_seq(R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2); radeon_emit(centroid_priority); radeon_emit(centroid_priority >> 32); @@ -156,10 +156,10 @@ static void si_emit_max_4_sample_locs(struct radeon_cmdbuf *cs, uint64_t centroi radeon_end(); } -static void si_emit_max_16_sample_locs(struct radeon_cmdbuf *cs, uint64_t centroid_priority, +static void si_emit_max_16_sample_locs(struct si_context *sctx, uint64_t centroid_priority, const uint32_t *sample_locs, unsigned num_samples) { - radeon_begin(cs); + radeon_begin(&sctx->gfx_cs); radeon_set_context_reg_seq(R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2); radeon_emit(centroid_priority); radeon_emit(centroid_priority >> 32); @@ -194,19 +194,19 @@ static void si_emit_sample_locations(struct si_context *sctx, unsigned index) switch (nr_samples) { default: case 1: - si_emit_max_4_sample_locs(cs, centroid_priority_1x, sample_locs_1x); + si_emit_max_4_sample_locs(sctx, centroid_priority_1x, sample_locs_1x); break; case 2: - si_emit_max_4_sample_locs(cs, centroid_priority_2x, sample_locs_2x); + si_emit_max_4_sample_locs(sctx, centroid_priority_2x, sample_locs_2x); break; case 4: - si_emit_max_4_sample_locs(cs, centroid_priority_4x, sample_locs_4x); + si_emit_max_4_sample_locs(sctx, centroid_priority_4x, sample_locs_4x); break; case 8: - si_emit_max_16_sample_locs(cs, centroid_priority_8x, sample_locs_8x, 8); + si_emit_max_16_sample_locs(sctx, centroid_priority_8x, sample_locs_8x, 8); break; case 16: - si_emit_max_16_sample_locs(cs, centroid_priority_16x, sample_locs_16x, 16); + si_emit_max_16_sample_locs(sctx, centroid_priority_16x, sample_locs_16x, 16); break; } sctx->sample_locs_num_samples = nr_samples;