diff --git a/src/asahi/lib/cmdbuf.xml b/src/asahi/lib/cmdbuf.xml
index ad39fcf5c6b..40c0c85baaa 100644
--- a/src/asahi/lib/cmdbuf.xml
+++ b/src/asahi/lib/cmdbuf.xml
@@ -863,10 +863,10 @@
-
+
-
+
@@ -884,13 +884,13 @@
-
+
-
+
@@ -915,9 +915,29 @@
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/src/asahi/lib/decode.c b/src/asahi/lib/decode.c
index 2bbfb25ed80..7847e63de7d 100644
--- a/src/asahi/lib/decode.c
+++ b/src/asahi/lib/decode.c
@@ -570,8 +570,8 @@ agxdecode_cdm(const uint8_t *map, uint64_t *link, bool verbose,
enum agx_cdm_block_type block_type = (map[3] >> 5);
switch (block_type) {
- case AGX_CDM_BLOCK_TYPE_HEADER: {
- size_t length = AGX_CDM_HEADER_LENGTH;
+ case AGX_CDM_BLOCK_TYPE_LAUNCH: {
+ size_t length = AGX_CDM_LAUNCH_LENGTH;
#define CDM_PRINT(STRUCT_NAME, human) \
do { \
@@ -580,11 +580,11 @@ agxdecode_cdm(const uint8_t *map, uint64_t *link, bool verbose,
length += AGX_CDM_##STRUCT_NAME##_LENGTH; \
} while (0);
- agx_unpack(agxdecode_dump_stream, map, CDM_HEADER, hdr);
+ agx_unpack(agxdecode_dump_stream, map, CDM_LAUNCH, hdr);
agxdecode_stateful(hdr.pipeline, "Pipeline", agxdecode_usc, verbose,
params, &hdr.sampler_state_register_count);
- DUMP_UNPACKED(CDM_HEADER, hdr, "Compute\n");
- map += AGX_CDM_HEADER_LENGTH;
+ DUMP_UNPACKED(CDM_LAUNCH, hdr, "Compute\n");
+ map += AGX_CDM_LAUNCH_LENGTH;
/* Added in G14X */
if (params->gpu_generation >= 14 && params->num_clusters_total > 1)
@@ -622,9 +622,9 @@ agxdecode_cdm(const uint8_t *map, uint64_t *link, bool verbose,
return STATE_DONE;
}
- case AGX_CDM_BLOCK_TYPE_LAUNCH: {
- DUMP_CL(CDM_LAUNCH, map, "Launch");
- return AGX_CDM_LAUNCH_LENGTH;
+ case AGX_CDM_BLOCK_TYPE_BARRIER: {
+ DUMP_CL(CDM_BARRIER, map, "Barrier");
+ return AGX_CDM_BARRIER_LENGTH;
}
default:
diff --git a/src/gallium/drivers/asahi/agx_state.c b/src/gallium/drivers/asahi/agx_state.c
index 94fae74190e..a9b6adecad9 100644
--- a/src/gallium/drivers/asahi/agx_state.c
+++ b/src/gallium/drivers/asahi/agx_state.c
@@ -4053,7 +4053,7 @@ agx_launch(struct agx_batch *batch, const struct pipe_grid_info *info,
/* TODO: Ensure space if we allow multiple kernels in a batch */
uint8_t *out = batch->cdm.current;
- agx_pack(out, CDM_HEADER, cfg) {
+ agx_pack(out, CDM_LAUNCH, cfg) {
if (info->indirect)
cfg.mode = AGX_CDM_MODE_INDIRECT_GLOBAL;
else
@@ -4068,7 +4068,7 @@ agx_launch(struct agx_batch *batch, const struct pipe_grid_info *info,
cfg.pipeline =
agx_build_pipeline(batch, cs, stage, info->variable_shared_mem);
}
- out += AGX_CDM_HEADER_LENGTH;
+ out += AGX_CDM_LAUNCH_LENGTH;
/* Added in G14X */
if (dev->params.gpu_generation >= 14 && dev->params.num_clusters_total > 1) {
@@ -4100,9 +4100,12 @@ agx_launch(struct agx_batch *batch, const struct pipe_grid_info *info,
}
out += AGX_CDM_LOCAL_SIZE_LENGTH;
- agx_pack(out, CDM_LAUNCH, cfg)
- ;
- out += AGX_CDM_LAUNCH_LENGTH;
+ agx_pack(out, CDM_BARRIER, cfg) {
+ cfg.unk_5 = true;
+ cfg.unk_6 = true;
+ cfg.unk_8 = true;
+ }
+ out += AGX_CDM_BARRIER_LENGTH;
batch->cdm.current = out;
assert(batch->cdm.current <= batch->cdm.end &&