From c1feccdd90ca90b0e6fecd2faa565da7c0fef628 Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Tue, 4 Jun 2024 19:27:26 -0700 Subject: [PATCH] intel/fs/gfx20+: Fix surface state address on extended descriptors for NIR scratch intrinsics. The r0.5 thread payload register contains Surface State Offset bits [27:6] as bits [31:10], so we need to shift the register right by 4 in order to get the surface state offset expected in ExBSO mode, which is the only extended descriptor encoding supported by the UGM shared function for SS addressing on Xe2+. Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/compiler/brw_eu_emit.c | 5 +++++ src/intel/compiler/brw_fs_nir.cpp | 4 ++++ src/intel/compiler/brw_lower_logical_sends.cpp | 2 ++ 3 files changed, 11 insertions(+) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 11bb27aa769..16f34ed50ef 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -1529,6 +1529,11 @@ brw_send_indirect_split_message(struct brw_codegen *p, const struct tgl_swsb swsb = brw_get_default_swsb(p); struct brw_reg addr = retype(brw_address_reg(2), BRW_TYPE_UD); + /* On Xe2+ ExBSO addressing is implicitly enabled for the UGM + * shared function. + */ + ex_bso |= (devinfo->ver >= 20 && sfid == GFX12_SFID_UGM); + brw_push_insn_state(p); brw_set_default_access_mode(p, BRW_ALIGN_1); brw_set_default_mask_control(p, BRW_MASK_DISABLE); diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 5b1db73877c..fb2c27bffb5 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -6740,6 +6740,8 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, fs_reg handle = component(ubld.vgrf(BRW_TYPE_UD), 0); ubld.AND(handle, retype(brw_vec1_grf(0, 5), BRW_TYPE_UD), brw_imm_ud(INTEL_MASK(31, 10))); + if (devinfo->ver >= 20) + ubld.SHR(handle, handle, brw_imm_ud(4)); srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GFX125_NON_BINDLESS); srcs[SURFACE_LOGICAL_SRC_SURFACE_HANDLE] = handle; } else { @@ -6800,6 +6802,8 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, fs_reg handle = component(ubld.vgrf(BRW_TYPE_UD), 0); ubld.AND(handle, retype(brw_vec1_grf(0, 5), BRW_TYPE_UD), brw_imm_ud(INTEL_MASK(31, 10))); + if (devinfo->ver >= 20) + ubld.SHR(handle, handle, brw_imm_ud(4)); srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GFX125_NON_BINDLESS); srcs[SURFACE_LOGICAL_SRC_SURFACE_HANDLE] = handle; } else { diff --git a/src/intel/compiler/brw_lower_logical_sends.cpp b/src/intel/compiler/brw_lower_logical_sends.cpp index c2e7c87302d..6985f81e37b 100644 --- a/src/intel/compiler/brw_lower_logical_sends.cpp +++ b/src/intel/compiler/brw_lower_logical_sends.cpp @@ -1858,6 +1858,8 @@ lower_lsc_block_logical_send(const fs_builder &bld, fs_inst *inst) ubld.AND(stateless_ex_desc, retype(brw_vec1_grf(0, 5), BRW_TYPE_UD), brw_imm_ud(INTEL_MASK(31, 10))); + if (devinfo->ver >= 20) + ubld.SHR(stateless_ex_desc, stateless_ex_desc, brw_imm_ud(4)); } fs_reg data;