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nv50/ir: fix surface lowering when values get shared accross operations

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With nir I encountered the case where the same value can be written to from
multiple surface operations. This caused some weird messups with the unions
as the def.rewrite operations caused unrelated instructions to get new their
value replaced as well.

In order to replace def.rewrite, we have to create a new temp value, write
to that one instead and move to the original value.

Fixes: 869e32593a ("gm107/ir: fix loading z offset for layered 3d image bindings")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11053>
This commit is contained in:
Karol Herbst 2020-06-16 20:17:55 +02:00
parent 561f9ae74b
commit c1f938b647
1 changed files with 15 additions and 13 deletions
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28
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
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@ -2328,15 +2328,15 @@ NVC0LoweringPass::insertOOBSurfaceOpResult(TexInstruction *su)
bld.setPosition(su, true); bld.setPosition(su, true);
for (unsigned i = 0; su->defExists(i); ++i) { for (unsigned i = 0; su->defExists(i); ++i) {
ValueDef &def = su->def(i); Value *def = su->getDef(i);
Value *newDef = bld.getSSA();
su->setDef(i, newDef);
Instruction *mov = bld.mkMov(bld.getSSA(), bld.loadImm(NULL, 0)); Instruction *mov = bld.mkMov(bld.getSSA(), bld.loadImm(NULL, 0));
assert(su->cc == CC_NOT_P); assert(su->cc == CC_NOT_P);
mov->setPredicate(CC_P, su->getPredicate()); mov->setPredicate(CC_P, su->getPredicate());
Instruction *uni = bld.mkOp2(OP_UNION, TYPE_U32, bld.getSSA(), NULL, mov->getDef(0)); Instruction *uni = bld.mkOp2(OP_UNION, TYPE_U32, bld.getSSA(), newDef, mov->getDef(0));
bld.mkMov(def, uni->getDef(0));
def.replace(uni->getDef(0), false);
uni->setSrc(0, def.get());
} }
} }
@ -2699,10 +2699,12 @@ NVC0LoweringPass::processSurfaceCoordsGM107(TexInstruction *su, Instruction *ret
for (unsigned i = 0; su->defExists(i); ++i) { for (unsigned i = 0; su->defExists(i); ++i) {
assert(i < 4); assert(i < 4);
ValueDef &def = su->def(i); Value *def = su->getDef(i);
Value *newDef = bld.getSSA();
ValueDef &def2 = su2d->def(i); ValueDef &def2 = su2d->def(i);
Instruction *mov = NULL; Instruction *mov = NULL;
su->setDef(i, newDef);
if (pred) { if (pred) {
mov = bld.mkMov(bld.getSSA(), bld.loadImm(NULL, 0)); mov = bld.mkMov(bld.getSSA(), bld.loadImm(NULL, 0));
mov->setPredicate(CC_P, pred->getDef(0)); mov->setPredicate(CC_P, pred->getDef(0));
@ -2710,11 +2712,10 @@ NVC0LoweringPass::processSurfaceCoordsGM107(TexInstruction *su, Instruction *ret
Instruction *uni = ret[i] = bld.mkOp2(OP_UNION, TYPE_U32, Instruction *uni = ret[i] = bld.mkOp2(OP_UNION, TYPE_U32,
bld.getSSA(), bld.getSSA(),
NULL, def2.get()); newDef, def2.get());
def.replace(uni->getDef(0), false);
uni->setSrc(0, def.get());
if (mov) if (mov)
uni->setSrc(2, mov->getDef(0)); uni->setSrc(2, mov->getDef(0));
bld.mkMov(def, uni->getDef(0));
} }
} else if (pred) { } else if (pred) {
// Create a UNION so that RA assigns the same registers // Create a UNION so that RA assigns the same registers
@ -2722,16 +2723,17 @@ NVC0LoweringPass::processSurfaceCoordsGM107(TexInstruction *su, Instruction *ret
for (unsigned i = 0; su->defExists(i); ++i) { for (unsigned i = 0; su->defExists(i); ++i) {
assert(i < 4); assert(i < 4);
ValueDef &def = su->def(i); Value *def = su->getDef(i);
Value *newDef = bld.getSSA();
su->setDef(i, newDef);
Instruction *mov = bld.mkMov(bld.getSSA(), bld.loadImm(NULL, 0)); Instruction *mov = bld.mkMov(bld.getSSA(), bld.loadImm(NULL, 0));
mov->setPredicate(CC_P, pred->getDef(0)); mov->setPredicate(CC_P, pred->getDef(0));
Instruction *uni = ret[i] = bld.mkOp2(OP_UNION, TYPE_U32, Instruction *uni = ret[i] = bld.mkOp2(OP_UNION, TYPE_U32,
bld.getSSA(), bld.getSSA(),
NULL, mov->getDef(0)); newDef, mov->getDef(0));
def.replace(uni->getDef(0), false); bld.mkMov(def, uni->getDef(0));
uni->setSrc(0, def.get());
} }
} }