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intel: Rename GENx prefix in macros to GFXx in source files

Browse source 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "GEN" -rIl src/intel/genxml | grep -E ".*py" |  xargs sed -ie "s/GEN\([%{]\)/GFX\1/g"
grep -E "[^_]GEN[[:digit:]]+" -rIl $SEARCH_PATH | grep -E ".*(\.c|\.h|\.y|\.l)" | xargs sed -ie "s/\([^_]\)GEN\([[:digit:]]\+\)/\1GFX\2/g"

Leave out renaming GFX12_CCS_E macros. They fall under renaming pattern like "_GEN[[:digit:]]+":
grep -E "GFX12_CCS_E" -rIl $SEARCH_PATH | xargs sed -ie "s/GFX12_CCS_E/GEN12_CCS_E/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
This commit is contained in:
Anuj Phogat 2021-03-29 15:16:59 -07:00 • committed by Marge Bot
parent 0cfe7e3968
commit c1f3a778de
79 changed files with 1824 additions and 1824 deletions
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2
src/intel/blorp/blorp_genX_exec.h
View file

@ -1384,7 +1384,7 @@ blorp_emit_memcpy(struct blorp_batch *batch,
/* IVB does not have a general purpose register for command streamer
* commands. Therefore, we use an alternate temporary register.
*/
#define BLORP_TEMP_REG 0x2440 /* GEN7_3DPRIM_BASE_VERTEX */
#define BLORP_TEMP_REG 0x2440 /* GFX7_3DPRIM_BASE_VERTEX */
blorp_emit(batch, GENX(MI_LOAD_REGISTER_MEM), load) {
load.RegisterAddress = BLORP_TEMP_REG;
load.MemoryAddress = src;

4
src/intel/common/mi_builder.h
View file

@ -582,7 +582,7 @@ mi_memset(struct mi_builder *b, __gen_address_type dst,
}
}
/* NOTE: On IVB, this function stomps GEN7_3DPRIM_BASE_VERTEX */
/* NOTE: On IVB, this function stomps GFX7_3DPRIM_BASE_VERTEX */
static inline void
mi_memcpy(struct mi_builder *b, __gen_address_type dst,
__gen_address_type src, uint32_t size)
@ -603,7 +603,7 @@ mi_memcpy(struct mi_builder *b, __gen_address_type dst,
/* IVB does not have a general purpose register for command streamer
* commands. Therefore, we use an alternate temporary register.
*/
struct mi_value tmp_reg = mi_reg32(0x2440); /* GEN7_3DPRIM_BASE_VERTEX */
struct mi_value tmp_reg = mi_reg32(0x2440); /* GFX7_3DPRIM_BASE_VERTEX */
mi_store(b, tmp_reg, src_val);
mi_store(b, dst_val, tmp_reg);
#endif

12
src/intel/common/tests/genxml_test.c
View file

@ -50,7 +50,7 @@ _test_combine_address(void *data, void *location,
static void
test_struct(struct intel_spec *spec) {
/* Fill struct fields and <group> tag */
struct GEN9_TEST_STRUCT test1 = {
struct GFX9_TEST_STRUCT test1 = {
.number1 = 5,
.number2 = 1234,
};
@ -60,8 +60,8 @@ test_struct(struct intel_spec *spec) {
}
/* Pack struct into a dw array */
uint32_t dw[GEN9_TEST_STRUCT_length];
GEN9_TEST_STRUCT_pack(NULL, dw, &test1);
uint32_t dw[GFX9_TEST_STRUCT_length];
GFX9_TEST_STRUCT_pack(NULL, dw, &test1);
/* Now decode the packed struct, and make sure it matches the original */
struct intel_group *group;
@ -94,7 +94,7 @@ test_struct(struct intel_spec *spec) {
static void
test_two_levels(struct intel_spec *spec) {
struct GEN9_STRUCT_TWO_LEVELS test;
struct GFX9_STRUCT_TWO_LEVELS test;
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 8; j++) {
@ -102,8 +102,8 @@ test_two_levels(struct intel_spec *spec) {
}
}
uint32_t dw[GEN9_STRUCT_TWO_LEVELS_length];
GEN9_STRUCT_TWO_LEVELS_pack(NULL, dw, &test);
uint32_t dw[GFX9_STRUCT_TWO_LEVELS_length];
GFX9_STRUCT_TWO_LEVELS_pack(NULL, dw, &test);
struct intel_group *group;
group = intel_spec_find_struct(spec, "STRUCT_TWO_LEVELS");

2
src/intel/common/tests/mi_builder_test.cpp
View file

@ -58,7 +58,7 @@ __gen_address_offset(address addr, uint64_t offset)
#if GFX_VERx10 >= 75
#define RSVD_TEMP_REG 0x2678 /* MI_ALU_REG15 */
#else
#define RSVD_TEMP_REG 0x2430 /* GEN7_3DPRIM_START_VERTEX */
#define RSVD_TEMP_REG 0x2430 /* GFX7_3DPRIM_START_VERTEX */
#endif
#define MI_BUILDER_NUM_ALLOC_GPRS 15
#define INPUT_DATA_OFFSET 0

2
src/intel/compiler/brw_clip_tri.c
View file

@ -250,7 +250,7 @@ load_clip_distance(struct brw_clip_compile *c, struct brw_indirect vtx,
}
/* Use mesa's clipping algorithms, translated to GEN4 assembly.
/* Use mesa's clipping algorithms, translated to GFX4 assembly.
*/
void brw_clip_tri( struct brw_clip_compile *c )
{

4
src/intel/compiler/brw_compiler.h
View file

@ -1288,9 +1288,9 @@ struct brw_gs_prog_data
unsigned control_data_header_size_hwords;
/**
* Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
* Format of the control data (either GFX7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
* if the control data is StreamID bits, or
* GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
* GFX7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
* Ignored if control_data_header_size is 0.
*/
unsigned control_data_format;

202
src/intel/compiler/brw_disasm.c
View file

@ -308,11 +308,11 @@ static const char *const gen6_sfid[16] = {
[BRW_SFID_MESSAGE_GATEWAY] = "gateway",
[BRW_SFID_URB] = "urb",
[BRW_SFID_THREAD_SPAWNER] = "thread_spawner",
[GEN6_SFID_DATAPORT_SAMPLER_CACHE] = "dp_sampler",
[GEN6_SFID_DATAPORT_RENDER_CACHE] = "render",
[GEN6_SFID_DATAPORT_CONSTANT_CACHE] = "const",
[GEN7_SFID_DATAPORT_DATA_CACHE] = "data",
[GEN7_SFID_PIXEL_INTERPOLATOR] = "pixel interp",
[GFX6_SFID_DATAPORT_SAMPLER_CACHE] = "dp_sampler",
[GFX6_SFID_DATAPORT_RENDER_CACHE] = "render",
[GFX6_SFID_DATAPORT_CONSTANT_CACHE] = "const",
[GFX7_SFID_DATAPORT_DATA_CACHE] = "data",
[GFX7_SFID_PIXEL_INTERPOLATOR] = "pixel interp",
[HSW_SFID_DATAPORT_DATA_CACHE_1] = "dp data 1",
[HSW_SFID_CRE] = "cre",
[GEN_RT_SFID_RAY_TRACE_ACCELERATOR] = "rt accel",
@ -357,37 +357,37 @@ static const char *const dp_write_port_msg_type[8] = {
static const char *const dp_rc_msg_type_gen6[16] = {
[BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ] = "OWORD block read",
[GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ] = "RT UNORM read",
[GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ] = "OWORD dual block read",
[GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ] = "media block read",
[GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ] =
[GFX6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ] = "RT UNORM read",
[GFX6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ] = "OWORD dual block read",
[GFX6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ] = "media block read",
[GFX6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ] =
"OWORD unaligned block read",
[GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ] = "DWORD scattered read",
[GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE] = "DWORD atomic write",
[GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE] = "OWORD block write",
[GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE] =
[GFX6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ] = "DWORD scattered read",
[GFX6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE] = "DWORD atomic write",
[GFX6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE] = "OWORD block write",
[GFX6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE] =
"OWORD dual block write",
[GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE] = "media block write",
[GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE] =
[GFX6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE] = "media block write",
[GFX6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE] =
"DWORD scattered write",
[GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE] = "RT write",
[GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE] = "streamed VB write",
[GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE] = "RT UNORM write",
[GFX6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE] = "RT write",
[GFX6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE] = "streamed VB write",
[GFX6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE] = "RT UNORM write",
};
static const char *const dp_rc_msg_type_gen7[16] = {
[GEN7_DATAPORT_RC_MEDIA_BLOCK_READ] = "media block read",
[GEN7_DATAPORT_RC_TYPED_SURFACE_READ] = "typed surface read",
[GEN7_DATAPORT_RC_TYPED_ATOMIC_OP] = "typed atomic op",
[GEN7_DATAPORT_RC_MEMORY_FENCE] = "memory fence",
[GEN7_DATAPORT_RC_MEDIA_BLOCK_WRITE] = "media block write",
[GEN7_DATAPORT_RC_RENDER_TARGET_WRITE] = "RT write",
[GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE] = "typed surface write"
[GFX7_DATAPORT_RC_MEDIA_BLOCK_READ] = "media block read",
[GFX7_DATAPORT_RC_TYPED_SURFACE_READ] = "typed surface read",
[GFX7_DATAPORT_RC_TYPED_ATOMIC_OP] = "typed atomic op",
[GFX7_DATAPORT_RC_MEMORY_FENCE] = "memory fence",
[GFX7_DATAPORT_RC_MEDIA_BLOCK_WRITE] = "media block write",
[GFX7_DATAPORT_RC_RENDER_TARGET_WRITE] = "RT write",
[GFX7_DATAPORT_RC_TYPED_SURFACE_WRITE] = "typed surface write"
};
static const char *const dp_rc_msg_type_gen9[16] = {
[GEN9_DATAPORT_RC_RENDER_TARGET_WRITE] = "RT write",
[GEN9_DATAPORT_RC_RENDER_TARGET_READ] = "RT read"
[GFX9_DATAPORT_RC_RENDER_TARGET_WRITE] = "RT write",
[GFX9_DATAPORT_RC_RENDER_TARGET_READ] = "RT read"
};
static const char *const *
@ -410,20 +410,20 @@ static const char *const m_rt_write_subtype[] = {
};
static const char *const dp_dc0_msg_type_gen7[16] = {
[GEN7_DATAPORT_DC_OWORD_BLOCK_READ] = "DC OWORD block read",
[GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ] =
[GFX7_DATAPORT_DC_OWORD_BLOCK_READ] = "DC OWORD block read",
[GFX7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ] =
"DC unaligned OWORD block read",
[GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ] = "DC OWORD dual block read",
[GEN7_DATAPORT_DC_DWORD_SCATTERED_READ] = "DC DWORD scattered read",
[GEN7_DATAPORT_DC_BYTE_SCATTERED_READ] = "DC byte scattered read",
[GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ] = "DC untyped surface read",
[GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP] = "DC untyped atomic",
[GEN7_DATAPORT_DC_MEMORY_FENCE] = "DC mfence",
[GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE] = "DC OWORD block write",
[GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE] = "DC OWORD dual block write",
[GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE] = "DC DWORD scatterd write",
[GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE] = "DC byte scattered write",
[GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE] = "DC untyped surface write",
[GFX7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ] = "DC OWORD dual block read",
[GFX7_DATAPORT_DC_DWORD_SCATTERED_READ] = "DC DWORD scattered read",
[GFX7_DATAPORT_DC_BYTE_SCATTERED_READ] = "DC byte scattered read",
[GFX7_DATAPORT_DC_UNTYPED_SURFACE_READ] = "DC untyped surface read",
[GFX7_DATAPORT_DC_UNTYPED_ATOMIC_OP] = "DC untyped atomic",
[GFX7_DATAPORT_DC_MEMORY_FENCE] = "DC mfence",
[GFX7_DATAPORT_DC_OWORD_BLOCK_WRITE] = "DC OWORD block write",
[GFX7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE] = "DC OWORD dual block write",
[GFX7_DATAPORT_DC_DWORD_SCATTERED_WRITE] = "DC DWORD scatterd write",
[GFX7_DATAPORT_DC_BYTE_SCATTERED_WRITE] = "DC byte scattered write",
[GFX7_DATAPORT_DC_UNTYPED_SURFACE_WRITE] = "DC untyped surface write",
};
static const char *const dp_dc1_msg_type_hsw[32] = {
@ -441,20 +441,20 @@ static const char *const dp_dc1_msg_type_hsw[32] = {
[HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2] =
"DC 4x2 atomic counter op",
[HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE] = "DC typed surface write",
[GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ] = "DC A64 scattered read",
[GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ] = "DC A64 untyped surface read",
[GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP] = "DC A64 untyped atomic op",
[GEN9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_READ] = "DC A64 oword block read",
[GEN9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_WRITE] = "DC A64 oword block write",
[GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE] = "DC A64 untyped surface write",
[GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE] = "DC A64 scattered write",
[GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP] =
[GFX9_DATAPORT_DC_PORT1_A64_SCATTERED_READ] = "DC A64 scattered read",
[GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ] = "DC A64 untyped surface read",
[GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP] = "DC A64 untyped atomic op",
[GFX9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_READ] = "DC A64 oword block read",
[GFX9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_WRITE] = "DC A64 oword block write",
[GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE] = "DC A64 untyped surface write",
[GFX8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE] = "DC A64 scattered write",
[GFX9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP] =
"DC untyped atomic float op",
[GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP] =
[GFX9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP] =
"DC A64 untyped atomic float op",
[GEN12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_INT_OP] =
[GFX12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_INT_OP] =
"DC A64 untyped atomic half-integer op",
[GEN12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_FLOAT_OP] =
[GFX12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_FLOAT_OP] =
"DC A64 untyped atomic half-float op",
};
@ -483,10 +483,10 @@ static const char *const aop_float[4] = {
};
static const char * const pixel_interpolator_msg_types[4] = {
[GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET] = "per_message_offset",
[GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE] = "sample_position",
[GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID] = "centroid",
[GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET] = "per_slot_offset",
[GFX7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET] = "per_message_offset",
[GFX7_PIXEL_INTERPOLATOR_LOC_SAMPLE] = "sample_position",
[GFX7_PIXEL_INTERPOLATOR_LOC_CENTROID] = "centroid",
[GFX7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET] = "per_slot_offset",
};
static const char *const math_function[16] = {
@ -503,8 +503,8 @@ static const char *const math_function[16] = {
[BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER] = "intdivmod",
[BRW_MATH_FUNCTION_INT_DIV_QUOTIENT] = "intdiv",
[BRW_MATH_FUNCTION_INT_DIV_REMAINDER] = "intmod",
[GEN8_MATH_FUNCTION_INVM] = "invm",
[GEN8_MATH_FUNCTION_RSQRTM] = "rsqrtm",
[GFX8_MATH_FUNCTION_INVM] = "invm",
[GFX8_MATH_FUNCTION_RSQRTM] = "rsqrtm",
};
static const char *const sync_function[16] = {
@ -545,11 +545,11 @@ static const char *const gen7_urb_opcode[] = {
[BRW_URB_OPCODE_WRITE_OWORD] = "write OWord",
[BRW_URB_OPCODE_READ_HWORD] = "read HWord",
[BRW_URB_OPCODE_READ_OWORD] = "read OWord",
[GEN7_URB_OPCODE_ATOMIC_MOV] = "atomic mov", /* Gen7+ */
[GEN7_URB_OPCODE_ATOMIC_INC] = "atomic inc", /* Gen7+ */
[GEN8_URB_OPCODE_ATOMIC_ADD] = "atomic add", /* Gen8+ */
[GEN8_URB_OPCODE_SIMD8_WRITE] = "SIMD8 write", /* Gen8+ */
[GEN8_URB_OPCODE_SIMD8_READ] = "SIMD8 read", /* Gen8+ */
[GFX7_URB_OPCODE_ATOMIC_MOV] = "atomic mov", /* Gen7+ */
[GFX7_URB_OPCODE_ATOMIC_INC] = "atomic inc", /* Gen7+ */
[GFX8_URB_OPCODE_ATOMIC_ADD] = "atomic add", /* Gen8+ */
[GFX8_URB_OPCODE_SIMD8_WRITE] = "SIMD8 write", /* Gen8+ */
[GFX8_URB_OPCODE_SIMD8_READ] = "SIMD8 read", /* Gen8+ */
/* [9-15] - reserved */
};
@ -575,29 +575,29 @@ static const char *const urb_complete[2] = {
};
static const char *const gen5_sampler_msg_type[] = {
[GEN5_SAMPLER_MESSAGE_SAMPLE] = "sample",
[GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS] = "sample_b",
[GEN5_SAMPLER_MESSAGE_SAMPLE_LOD] = "sample_l",
[GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE] = "sample_c",
[GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS] = "sample_d",
[GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE] = "sample_b_c",
[GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE] = "sample_l_c",
[GEN5_SAMPLER_MESSAGE_SAMPLE_LD] = "ld",
[GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4] = "gather4",
[GEN5_SAMPLER_MESSAGE_LOD] = "lod",
[GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO] = "resinfo",
[GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO] = "sampleinfo",
[GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C] = "gather4_c",
[GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO] = "gather4_po",
[GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C] = "gather4_po_c",
[GFX5_SAMPLER_MESSAGE_SAMPLE] = "sample",
[GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS] = "sample_b",
[GFX5_SAMPLER_MESSAGE_SAMPLE_LOD] = "sample_l",
[GFX5_SAMPLER_MESSAGE_SAMPLE_COMPARE] = "sample_c",
[GFX5_SAMPLER_MESSAGE_SAMPLE_DERIVS] = "sample_d",
[GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE] = "sample_b_c",
[GFX5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE] = "sample_l_c",
[GFX5_SAMPLER_MESSAGE_SAMPLE_LD] = "ld",
[GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4] = "gather4",
[GFX5_SAMPLER_MESSAGE_LOD] = "lod",
[GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO] = "resinfo",
[GFX6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO] = "sampleinfo",
[GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C] = "gather4_c",
[GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO] = "gather4_po",
[GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C] = "gather4_po_c",
[HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE] = "sample_d_c",
[GEN9_SAMPLER_MESSAGE_SAMPLE_LZ] = "sample_lz",
[GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ] = "sample_c_lz",
[GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ] = "ld_lz",
[GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W] = "ld2dms_w",
[GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS] = "ld_mcs",
[GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS] = "ld2dms",
[GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS] = "ld2dss",
[GFX9_SAMPLER_MESSAGE_SAMPLE_LZ] = "sample_lz",
[GFX9_SAMPLER_MESSAGE_SAMPLE_C_LZ] = "sample_c_lz",
[GFX9_SAMPLER_MESSAGE_SAMPLE_LD_LZ] = "ld_lz",
[GFX9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W] = "ld2dms_w",
[GFX7_SAMPLER_MESSAGE_SAMPLE_LD_MCS] = "ld_mcs",
[GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DMS] = "ld2dms",
[GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DSS] = "ld2dss",
};
static const char *const gen5_sampler_simd_mode[4] = {
@ -1060,7 +1060,7 @@ vstride_from_align1_3src_hstride(enum gen10_align1_3src_src_horizontal_stride hs
}
}
/* From "GEN10 Regioning Rules for Align1 Ternary Operations" in the
/* From "GFX10 Regioning Rules for Align1 Ternary Operations" in the
* "Register Region Restrictions" documentation
*/
static enum brw_width
@ -1917,8 +1917,8 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
string(file, ")");
}
break;
case GEN6_SFID_DATAPORT_SAMPLER_CACHE:
case GEN6_SFID_DATAPORT_CONSTANT_CACHE:
case GFX6_SFID_DATAPORT_SAMPLER_CACHE:
case GFX6_SFID_DATAPORT_CONSTANT_CACHE:
/* aka BRW_SFID_DATAPORT_READ on Gen4-5 */
if (devinfo->ver >= 6) {
format(file, " (%u, %u, %u, %u)",
@ -1943,7 +1943,7 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
}
break;
case GEN6_SFID_DATAPORT_RENDER_CACHE: {
case GFX6_SFID_DATAPORT_RENDER_CACHE: {
/* aka BRW_SFID_DATAPORT_WRITE on Gen4-5 */
unsigned msg_type = brw_dp_write_desc_msg_type(devinfo, imm_desc);
@ -1951,7 +1951,7 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
dp_rc_msg_type(devinfo), msg_type, &space);
bool is_rt_write = msg_type ==
(devinfo->ver >= 6 ? GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
(devinfo->ver >= 6 ? GFX6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
: BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE);
if (is_rt_write) {
@ -1991,8 +1991,8 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
string(file, " per-slot");
}
if (opcode == GEN8_URB_OPCODE_SIMD8_WRITE ||
opcode == GEN8_URB_OPCODE_SIMD8_READ) {
if (opcode == GFX8_URB_OPCODE_SIMD8_WRITE ||
opcode == GFX8_URB_OPCODE_SIMD8_READ) {
if (brw_inst_urb_channel_mask_present(devinfo, inst))
string(file, " masked");
} else {
@ -2021,7 +2021,7 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
gen7_gateway_subfuncid[brw_inst_gateway_subfuncid(devinfo, inst)]);
break;
case GEN7_SFID_DATAPORT_DATA_CACHE:
case GFX7_SFID_DATAPORT_DATA_CACHE:
if (devinfo->ver >= 7) {
format(file, " (");
@ -2033,7 +2033,7 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
brw_dp_desc_binding_table_index(devinfo, imm_desc));
switch (brw_inst_dp_msg_type(devinfo, inst)) {
case GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP:
case GFX7_DATAPORT_DC_UNTYPED_ATOMIC_OP:
control(file, "atomic op", aop,
brw_dp_desc_msg_control(devinfo, imm_desc) & 0xf,
&space);
@ -2070,24 +2070,24 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2:
case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2:
case HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2:
case GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP:
case GEN12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_INT_OP:
case GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP:
case GFX12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_INT_OP:
control(file, "atomic op", aop, msg_ctrl & 0xf, &space);
break;
case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ:
case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE:
case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ:
case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE:
case GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE:
case GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ: {
case GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE:
case GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ: {
static const char *simd_modes[] = { "4x2", "16", "8" };
format(file, "SIMD%s, Mask = 0x%x",
simd_modes[msg_ctrl >> 4], msg_ctrl & 0xf);
break;
}
case GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP:
case GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP:
case GEN12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_FLOAT_OP:
case GFX9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP:
case GFX9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP:
case GFX12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_FLOAT_OP:
format(file, "SIMD%d,", (msg_ctrl & (1 << 4)) ? 8 : 16);
control(file, "atomic float op", aop_float, msg_ctrl & 0xf,
&space);
@ -2102,7 +2102,7 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
break;
}
case GEN7_SFID_PIXEL_INTERPOLATOR:
case GFX7_SFID_PIXEL_INTERPOLATOR:
if (devinfo->ver >= 7) {
format(file, " (%s, %s, 0x%02"PRIx64")",
brw_inst_pi_nopersp(devinfo, inst) ? "linear" : "persp",

166
src/intel/compiler/brw_eu.cpp
View file

@ -591,80 +591,80 @@ brw_disassemble(const struct gen_device_info *devinfo,
static const struct opcode_desc opcode_descs[] = {
/* IR, HW, name, nsrc, ndst, gens */
{ BRW_OPCODE_ILLEGAL, 0, "illegal", 0, 0, GEN_ALL },
{ BRW_OPCODE_SYNC, 1, "sync", 1, 0, GEN_GE(GEN12) },
{ BRW_OPCODE_MOV, 1, "mov", 1, 1, GEN_LT(GEN12) },
{ BRW_OPCODE_MOV, 97, "mov", 1, 1, GEN_GE(GEN12) },
{ BRW_OPCODE_SEL, 2, "sel", 2, 1, GEN_LT(GEN12) },
{ BRW_OPCODE_SEL, 98, "sel", 2, 1, GEN_GE(GEN12) },
{ BRW_OPCODE_MOVI, 3, "movi", 2, 1, GEN_GE(GEN45) & GEN_LT(GEN12) },
{ BRW_OPCODE_MOVI, 99, "movi", 2, 1, GEN_GE(GEN12) },
{ BRW_OPCODE_NOT, 4, "not", 1, 1, GEN_LT(GEN12) },
{ BRW_OPCODE_NOT, 100, "not", 1, 1, GEN_GE(GEN12) },
{ BRW_OPCODE_AND, 5, "and", 2, 1, GEN_LT(GEN12) },
{ BRW_OPCODE_AND, 101, "and", 2, 1, GEN_GE(GEN12) },
{ BRW_OPCODE_OR, 6, "or", 2, 1, GEN_LT(GEN12) },
{ BRW_OPCODE_OR, 102, "or", 2, 1, GEN_GE(GEN12) },
{ BRW_OPCODE_XOR, 7, "xor", 2, 1, GEN_LT(GEN12) },
{ BRW_OPCODE_XOR, 103, "xor", 2, 1, GEN_GE(GEN12) },
{ BRW_OPCODE_SHR, 8, "shr", 2, 1, GEN_LT(GEN12) },
{ BRW_OPCODE_SHR, 104, "shr", 2, 1, GEN_GE(GEN12) },
{ BRW_OPCODE_SHL, 9, "shl", 2, 1, GEN_LT(GEN12) },
{ BRW_OPCODE_SHL, 105, "shl", 2, 1, GEN_GE(GEN12) },
{ BRW_OPCODE_DIM, 10, "dim", 1, 1, GEN75 },
{ BRW_OPCODE_SMOV, 10, "smov", 0, 0, GEN_GE(GEN8) & GEN_LT(GEN12) },
{ BRW_OPCODE_SMOV, 106, "smov", 0, 0, GEN_GE(GEN12) },
{ BRW_OPCODE_ASR, 12, "asr", 2, 1, GEN_LT(GEN12) },
{ BRW_OPCODE_ASR, 108, "asr", 2, 1, GEN_GE(GEN12) },
{ BRW_OPCODE_ROR, 14, "ror", 2, 1, GEN11 },
{ BRW_OPCODE_ROR, 110, "ror", 2, 1, GEN_GE(GEN12) },
{ BRW_OPCODE_ROL, 15, "rol", 2, 1, GEN11 },
{ BRW_OPCODE_ROL, 111, "rol", 2, 1, GEN_GE(GEN12) },
{ BRW_OPCODE_CMP, 16, "cmp", 2, 1, GEN_LT(GEN12) },
{ BRW_OPCODE_CMP, 112, "cmp", 2, 1, GEN_GE(GEN12) },
{ BRW_OPCODE_CMPN, 17, "cmpn", 2, 1, GEN_LT(GEN12) },
{ BRW_OPCODE_CMPN, 113, "cmpn", 2, 1, GEN_GE(GEN12) },
{ BRW_OPCODE_CSEL, 18, "csel", 3, 1, GEN_GE(GEN8) & GEN_LT(GEN12) },
{ BRW_OPCODE_CSEL, 114, "csel", 3, 1, GEN_GE(GEN12) },
{ BRW_OPCODE_F32TO16, 19, "f32to16", 1, 1, GEN7 | GEN75 },
{ BRW_OPCODE_F16TO32, 20, "f16to32", 1, 1, GEN7 | GEN75 },
{ BRW_OPCODE_BFREV, 23, "bfrev", 1, 1, GEN_GE(GEN7) & GEN_LT(GEN12) },
{ BRW_OPCODE_BFREV, 119, "bfrev", 1, 1, GEN_GE(GEN12) },
{ BRW_OPCODE_BFE, 24, "bfe", 3, 1, GEN_GE(GEN7) & GEN_LT(GEN12) },
{ BRW_OPCODE_BFE, 120, "bfe", 3, 1, GEN_GE(GEN12) },
{ BRW_OPCODE_BFI1, 25, "bfi1", 2, 1, GEN_GE(GEN7) & GEN_LT(GEN12) },
{ BRW_OPCODE_BFI1, 121, "bfi1", 2, 1, GEN_GE(GEN12) },
{ BRW_OPCODE_BFI2, 26, "bfi2", 3, 1, GEN_GE(GEN7) & GEN_LT(GEN12) },
{ BRW_OPCODE_BFI2, 122, "bfi2", 3, 1, GEN_GE(GEN12) },
{ BRW_OPCODE_SYNC, 1, "sync", 1, 0, GEN_GE(GFX12) },
{ BRW_OPCODE_MOV, 1, "mov", 1, 1, GEN_LT(GFX12) },
{ BRW_OPCODE_MOV, 97, "mov", 1, 1, GEN_GE(GFX12) },
{ BRW_OPCODE_SEL, 2, "sel", 2, 1, GEN_LT(GFX12) },
{ BRW_OPCODE_SEL, 98, "sel", 2, 1, GEN_GE(GFX12) },
{ BRW_OPCODE_MOVI, 3, "movi", 2, 1, GEN_GE(GFX45) & GEN_LT(GFX12) },
{ BRW_OPCODE_MOVI, 99, "movi", 2, 1, GEN_GE(GFX12) },
{ BRW_OPCODE_NOT, 4, "not", 1, 1, GEN_LT(GFX12) },
{ BRW_OPCODE_NOT, 100, "not", 1, 1, GEN_GE(GFX12) },
{ BRW_OPCODE_AND, 5, "and", 2, 1, GEN_LT(GFX12) },
{ BRW_OPCODE_AND, 101, "and", 2, 1, GEN_GE(GFX12) },
{ BRW_OPCODE_OR, 6, "or", 2, 1, GEN_LT(GFX12) },
{ BRW_OPCODE_OR, 102, "or", 2, 1, GEN_GE(GFX12) },
{ BRW_OPCODE_XOR, 7, "xor", 2, 1, GEN_LT(GFX12) },
{ BRW_OPCODE_XOR, 103, "xor", 2, 1, GEN_GE(GFX12) },
{ BRW_OPCODE_SHR, 8, "shr", 2, 1, GEN_LT(GFX12) },
{ BRW_OPCODE_SHR, 104, "shr", 2, 1, GEN_GE(GFX12) },
{ BRW_OPCODE_SHL, 9, "shl", 2, 1, GEN_LT(GFX12) },
{ BRW_OPCODE_SHL, 105, "shl", 2, 1, GEN_GE(GFX12) },
{ BRW_OPCODE_DIM, 10, "dim", 1, 1, GFX75 },
{ BRW_OPCODE_SMOV, 10, "smov", 0, 0, GEN_GE(GFX8) & GEN_LT(GFX12) },
{ BRW_OPCODE_SMOV, 106, "smov", 0, 0, GEN_GE(GFX12) },
{ BRW_OPCODE_ASR, 12, "asr", 2, 1, GEN_LT(GFX12) },
{ BRW_OPCODE_ASR, 108, "asr", 2, 1, GEN_GE(GFX12) },
{ BRW_OPCODE_ROR, 14, "ror", 2, 1, GFX11 },
{ BRW_OPCODE_ROR, 110, "ror", 2, 1, GEN_GE(GFX12) },
{ BRW_OPCODE_ROL, 15, "rol", 2, 1, GFX11 },
{ BRW_OPCODE_ROL, 111, "rol", 2, 1, GEN_GE(GFX12) },
{ BRW_OPCODE_CMP, 16, "cmp", 2, 1, GEN_LT(GFX12) },
{ BRW_OPCODE_CMP, 112, "cmp", 2, 1, GEN_GE(GFX12) },
{ BRW_OPCODE_CMPN, 17, "cmpn", 2, 1, GEN_LT(GFX12) },
{ BRW_OPCODE_CMPN, 113, "cmpn", 2, 1, GEN_GE(GFX12) },
{ BRW_OPCODE_CSEL, 18, "csel", 3, 1, GEN_GE(GFX8) & GEN_LT(GFX12) },
{ BRW_OPCODE_CSEL, 114, "csel", 3, 1, GEN_GE(GFX12) },
{ BRW_OPCODE_F32TO16, 19, "f32to16", 1, 1, GFX7 | GFX75 },
{ BRW_OPCODE_F16TO32, 20, "f16to32", 1, 1, GFX7 | GFX75 },
{ BRW_OPCODE_BFREV, 23, "bfrev", 1, 1, GEN_GE(GFX7) & GEN_LT(GFX12) },
{ BRW_OPCODE_BFREV, 119, "bfrev", 1, 1, GEN_GE(GFX12) },
{ BRW_OPCODE_BFE, 24, "bfe", 3, 1, GEN_GE(GFX7) & GEN_LT(GFX12) },
{ BRW_OPCODE_BFE, 120, "bfe", 3, 1, GEN_GE(GFX12) },
{ BRW_OPCODE_BFI1, 25, "bfi1", 2, 1, GEN_GE(GFX7) & GEN_LT(GFX12) },
{ BRW_OPCODE_BFI1, 121, "bfi1", 2, 1, GEN_GE(GFX12) },
{ BRW_OPCODE_BFI2, 26, "bfi2", 3, 1, GEN_GE(GFX7) & GEN_LT(GFX12) },
{ BRW_OPCODE_BFI2, 122, "bfi2", 3, 1, GEN_GE(GFX12) },
{ BRW_OPCODE_JMPI, 32, "jmpi", 0, 0, GEN_ALL },
{ BRW_OPCODE_BRD, 33, "brd", 0, 0, GEN_GE(GEN7) },
{ BRW_OPCODE_BRD, 33, "brd", 0, 0, GEN_GE(GFX7) },
{ BRW_OPCODE_IF, 34, "if", 0, 0, GEN_ALL },
{ BRW_OPCODE_IFF, 35, "iff", 0, 0, GEN_LE(GEN5) },
{ BRW_OPCODE_BRC, 35, "brc", 0, 0, GEN_GE(GEN7) },
{ BRW_OPCODE_IFF, 35, "iff", 0, 0, GEN_LE(GFX5) },
{ BRW_OPCODE_BRC, 35, "brc", 0, 0, GEN_GE(GFX7) },
{ BRW_OPCODE_ELSE, 36, "else", 0, 0, GEN_ALL },
{ BRW_OPCODE_ENDIF, 37, "endif", 0, 0, GEN_ALL },
{ BRW_OPCODE_DO, 38, "do", 0, 0, GEN_LE(GEN5) },
{ BRW_OPCODE_CASE, 38, "case", 0, 0, GEN6 },
{ BRW_OPCODE_DO, 38, "do", 0, 0, GEN_LE(GFX5) },
{ BRW_OPCODE_CASE, 38, "case", 0, 0, GFX6 },
{ BRW_OPCODE_WHILE, 39, "while", 0, 0, GEN_ALL },
{ BRW_OPCODE_BREAK, 40, "break", 0, 0, GEN_ALL },
{ BRW_OPCODE_CONTINUE, 41, "cont", 0, 0, GEN_ALL },
{ BRW_OPCODE_HALT, 42, "halt", 0, 0, GEN_ALL },
{ BRW_OPCODE_CALLA, 43, "calla", 0, 0, GEN_GE(GEN75) },
{ BRW_OPCODE_MSAVE, 44, "msave", 0, 0, GEN_LE(GEN5) },
{ BRW_OPCODE_CALL, 44, "call", 0, 0, GEN_GE(GEN6) },
{ BRW_OPCODE_MREST, 45, "mrest", 0, 0, GEN_LE(GEN5) },
{ BRW_OPCODE_RET, 45, "ret", 0, 0, GEN_GE(GEN6) },
{ BRW_OPCODE_PUSH, 46, "push", 0, 0, GEN_LE(GEN5) },
{ BRW_OPCODE_FORK, 46, "fork", 0, 0, GEN6 },
{ BRW_OPCODE_GOTO, 46, "goto", 0, 0, GEN_GE(GEN8) },
{ BRW_OPCODE_POP, 47, "pop", 2, 0, GEN_LE(GEN5) },
{ BRW_OPCODE_WAIT, 48, "wait", 0, 1, GEN_LT(GEN12) },
{ BRW_OPCODE_SEND, 49, "send", 1, 1, GEN_LT(GEN12) },
{ BRW_OPCODE_SENDC, 50, "sendc", 1, 1, GEN_LT(GEN12) },
{ BRW_OPCODE_SEND, 49, "send", 2, 1, GEN_GE(GEN12) },
{ BRW_OPCODE_SENDC, 50, "sendc", 2, 1, GEN_GE(GEN12) },
{ BRW_OPCODE_SENDS, 51, "sends", 2, 1, GEN_GE(GEN9) & GEN_LT(GEN12) },
{ BRW_OPCODE_SENDSC, 52, "sendsc", 2, 1, GEN_GE(GEN9) & GEN_LT(GEN12) },
{ BRW_OPCODE_MATH, 56, "math", 2, 1, GEN_GE(GEN6) },
{ BRW_OPCODE_CALLA, 43, "calla", 0, 0, GEN_GE(GFX75) },
{ BRW_OPCODE_MSAVE, 44, "msave", 0, 0, GEN_LE(GFX5) },
{ BRW_OPCODE_CALL, 44, "call", 0, 0, GEN_GE(GFX6) },
{ BRW_OPCODE_MREST, 45, "mrest", 0, 0, GEN_LE(GFX5) },
{ BRW_OPCODE_RET, 45, "ret", 0, 0, GEN_GE(GFX6) },
{ BRW_OPCODE_PUSH, 46, "push", 0, 0, GEN_LE(GFX5) },
{ BRW_OPCODE_FORK, 46, "fork", 0, 0, GFX6 },
{ BRW_OPCODE_GOTO, 46, "goto", 0, 0, GEN_GE(GFX8) },
{ BRW_OPCODE_POP, 47, "pop", 2, 0, GEN_LE(GFX5) },
{ BRW_OPCODE_WAIT, 48, "wait", 0, 1, GEN_LT(GFX12) },
{ BRW_OPCODE_SEND, 49, "send", 1, 1, GEN_LT(GFX12) },
{ BRW_OPCODE_SENDC, 50, "sendc", 1, 1, GEN_LT(GFX12) },
{ BRW_OPCODE_SEND, 49, "send", 2, 1, GEN_GE(GFX12) },
{ BRW_OPCODE_SENDC, 50, "sendc", 2, 1, GEN_GE(GFX12) },
{ BRW_OPCODE_SENDS, 51, "sends", 2, 1, GEN_GE(GFX9) & GEN_LT(GFX12) },
{ BRW_OPCODE_SENDSC, 52, "sendsc", 2, 1, GEN_GE(GFX9) & GEN_LT(GFX12) },
{ BRW_OPCODE_MATH, 56, "math", 2, 1, GEN_GE(GFX6) },
{ BRW_OPCODE_ADD, 64, "add", 2, 1, GEN_ALL },
{ BRW_OPCODE_MUL, 65, "mul", 2, 1, GEN_ALL },
{ BRW_OPCODE_AVG, 66, "avg", 2, 1, GEN_ALL },
@ -676,25 +676,25 @@ static const struct opcode_desc opcode_descs[] = {
{ BRW_OPCODE_MAC, 72, "mac", 2, 1, GEN_ALL },
{ BRW_OPCODE_MACH, 73, "mach", 2, 1, GEN_ALL },
{ BRW_OPCODE_LZD, 74, "lzd", 1, 1, GEN_ALL },
{ BRW_OPCODE_FBH, 75, "fbh", 1, 1, GEN_GE(GEN7) },
{ BRW_OPCODE_FBL, 76, "fbl", 1, 1, GEN_GE(GEN7) },
{ BRW_OPCODE_CBIT, 77, "cbit", 1, 1, GEN_GE(GEN7) },
{ BRW_OPCODE_ADDC, 78, "addc", 2, 1, GEN_GE(GEN7) },
{ BRW_OPCODE_SUBB, 79, "subb", 2, 1, GEN_GE(GEN7) },
{ BRW_OPCODE_FBH, 75, "fbh", 1, 1, GEN_GE(GFX7) },
{ BRW_OPCODE_FBL, 76, "fbl", 1, 1, GEN_GE(GFX7) },
{ BRW_OPCODE_CBIT, 77, "cbit", 1, 1, GEN_GE(GFX7) },
{ BRW_OPCODE_ADDC, 78, "addc", 2, 1, GEN_GE(GFX7) },
{ BRW_OPCODE_SUBB, 79, "subb", 2, 1, GEN_GE(GFX7) },
{ BRW_OPCODE_SAD2, 80, "sad2", 2, 1, GEN_ALL },
{ BRW_OPCODE_SADA2, 81, "sada2", 2, 1, GEN_ALL },
{ BRW_OPCODE_DP4, 84, "dp4", 2, 1, GEN_LT(GEN11) },
{ BRW_OPCODE_DPH, 85, "dph", 2, 1, GEN_LT(GEN11) },
{ BRW_OPCODE_DP3, 86, "dp3", 2, 1, GEN_LT(GEN11) },
{ BRW_OPCODE_DP2, 87, "dp2", 2, 1, GEN_LT(GEN11) },
{ BRW_OPCODE_LINE, 89, "line", 2, 1, GEN_LE(GEN10) },
{ BRW_OPCODE_PLN, 90, "pln", 2, 1, GEN_GE(GEN45) & GEN_LE(GEN10) },
{ BRW_OPCODE_MAD, 91, "mad", 3, 1, GEN_GE(GEN6) },
{ BRW_OPCODE_LRP, 92, "lrp", 3, 1, GEN_GE(GEN6) & GEN_LE(GEN10) },
{ BRW_OPCODE_MADM, 93, "madm", 3, 1, GEN_GE(GEN8) },
{ BRW_OPCODE_NENOP, 125, "nenop", 0, 0, GEN45 },
{ BRW_OPCODE_NOP, 126, "nop", 0, 0, GEN_LT(GEN12) },
{ BRW_OPCODE_NOP, 96, "nop", 0, 0, GEN_GE(GEN12) }
{ BRW_OPCODE_DP4, 84, "dp4", 2, 1, GEN_LT(GFX11) },
{ BRW_OPCODE_DPH, 85, "dph", 2, 1, GEN_LT(GFX11) },
{ BRW_OPCODE_DP3, 86, "dp3", 2, 1, GEN_LT(GFX11) },
{ BRW_OPCODE_DP2, 87, "dp2", 2, 1, GEN_LT(GFX11) },
{ BRW_OPCODE_LINE, 89, "line", 2, 1, GEN_LE(GFX10) },
{ BRW_OPCODE_PLN, 90, "pln", 2, 1, GEN_GE(GFX45) & GEN_LE(GFX10) },
{ BRW_OPCODE_MAD, 91, "mad", 3, 1, GEN_GE(GFX6) },
{ BRW_OPCODE_LRP, 92, "lrp", 3, 1, GEN_GE(GFX6) & GEN_LE(GFX10) },
{ BRW_OPCODE_MADM, 93, "madm", 3, 1, GEN_GE(GFX8) },
{ BRW_OPCODE_NENOP, 125, "nenop", 0, 0, GFX45 },
{ BRW_OPCODE_NOP, 126, "nop", 0, 0, GEN_LT(GFX12) },
{ BRW_OPCODE_NOP, 96, "nop", 0, 0, GEN_GE(GFX12) }
};
/**

62
src/intel/compiler/brw_eu.h
View file

@ -636,7 +636,7 @@ brw_dp_untyped_atomic_desc(const struct gen_device_info *devinfo,
msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2;
}
} else {
msg_type = GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP;
msg_type = GFX7_DATAPORT_DC_UNTYPED_ATOMIC_OP;
}
const unsigned msg_control =
@ -657,7 +657,7 @@ brw_dp_untyped_atomic_float_desc(const struct gen_device_info *devinfo,
assert(devinfo->ver >= 9);
assert(exec_size > 0);
const unsigned msg_type = GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP;
const unsigned msg_type = GFX9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP;
const unsigned msg_control =
SET_BITS(atomic_op, 1, 0) |
@ -687,14 +687,14 @@ brw_dp_untyped_surface_rw_desc(const struct gen_device_info *devinfo,
if (devinfo->ver >= 8 || devinfo->is_haswell) {
msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE;
} else {
msg_type = GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE;
msg_type = GFX7_DATAPORT_DC_UNTYPED_SURFACE_WRITE;
}
} else {
/* Read */
if (devinfo->ver >= 8 || devinfo->is_haswell) {
msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ;
} else {
msg_type = GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ;
msg_type = GFX7_DATAPORT_DC_UNTYPED_SURFACE_READ;
}
}
@ -718,11 +718,11 @@ brw_mdc_ds(unsigned bit_size)
{
switch (bit_size) {
case 8:
return GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE;
return GFX7_BYTE_SCATTERED_DATA_ELEMENT_BYTE;
case 16:
return GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD;
return GFX7_BYTE_SCATTERED_DATA_ELEMENT_WORD;
case 32:
return GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD;
return GFX7_BYTE_SCATTERED_DATA_ELEMENT_DWORD;
default:
unreachable("Unsupported bit_size for byte scattered messages");
}
@ -759,13 +759,13 @@ brw_dp_dword_scattered_rw_desc(const struct gen_device_info *devinfo,
unsigned msg_type;
if (write) {
if (devinfo->ver >= 6) {
msg_type = GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE;
msg_type = GFX6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE;
} else {
msg_type = BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE;
}
} else {
if (devinfo->ver >= 7) {
msg_type = GEN7_DATAPORT_DC_DWORD_SCATTERED_READ;
msg_type = GFX7_DATAPORT_DC_DWORD_SCATTERED_READ;
} else if (devinfo->ver > 4 || devinfo->is_g4x) {
msg_type = G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ;
} else {
@ -790,9 +790,9 @@ brw_dp_oword_block_rw_desc(const struct gen_device_info *devinfo,
assert(!write || align_16B);
const unsigned msg_type =
write ? GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE :
align_16B ? GEN7_DATAPORT_DC_OWORD_BLOCK_READ :
GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ;
write ? GFX7_DATAPORT_DC_OWORD_BLOCK_WRITE :
align_16B ? GFX7_DATAPORT_DC_OWORD_BLOCK_READ :
GFX7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ;
const unsigned msg_control =
SET_BITS(BRW_DATAPORT_OWORD_BLOCK_DWORDS(num_dwords), 2, 0);
@ -810,8 +810,8 @@ brw_dp_a64_untyped_surface_rw_desc(const struct gen_device_info *devinfo,
assert(devinfo->ver >= 8);
unsigned msg_type =
write ? GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE :
GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ;
write ? GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE :
GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ;
/* See also MDC_SM3 in the SKL PRM Vol 2d. */
const unsigned simd_mode = exec_size == 0 ? 0 : /* SIMD4x2 */
@ -821,7 +821,7 @@ brw_dp_a64_untyped_surface_rw_desc(const struct gen_device_info *devinfo,
SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
SET_BITS(simd_mode, 5, 4);
return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
return brw_dp_desc(devinfo, GFX8_BTI_STATELESS_NON_COHERENT,
msg_type, msg_control);
}
@ -835,14 +835,14 @@ brw_dp_a64_oword_block_rw_desc(const struct gen_device_info *devinfo,
assert(!write || align_16B);
unsigned msg_type =
write ? GEN9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_WRITE :
GEN9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_READ;
write ? GFX9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_WRITE :
GFX9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_READ;
unsigned msg_control =
SET_BITS(!align_16B, 4, 3) |
SET_BITS(BRW_DATAPORT_OWORD_BLOCK_DWORDS(num_dwords), 2, 0);
return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
return brw_dp_desc(devinfo, GFX8_BTI_STATELESS_NON_COHERENT,
msg_type, msg_control);
}
@ -873,15 +873,15 @@ brw_dp_a64_byte_scattered_rw_desc(const struct gen_device_info *devinfo,
assert(devinfo->ver >= 8);
unsigned msg_type =
write ? GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE :
GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ;
write ? GFX8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE :
GFX9_DATAPORT_DC_PORT1_A64_SCATTERED_READ;
const unsigned msg_control =
SET_BITS(GEN8_A64_SCATTERED_SUBTYPE_BYTE, 1, 0) |
SET_BITS(GFX8_A64_SCATTERED_SUBTYPE_BYTE, 1, 0) |
SET_BITS(brw_mdc_a64_ds(bit_size / 8), 3, 2) |
SET_BITS(exec_size == 16, 4, 4);
return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
return brw_dp_desc(devinfo, GFX8_BTI_STATELESS_NON_COHERENT,
msg_type, msg_control);
}
@ -898,15 +898,15 @@ brw_dp_a64_untyped_atomic_desc(const struct gen_device_info *devinfo,
assert(devinfo->ver >= 12 || bit_size >= 32);
const unsigned msg_type = bit_size == 16 ?
GEN12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_INT_OP :
GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP;
GFX12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_INT_OP :
GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP;
const unsigned msg_control =
SET_BITS(atomic_op, 3, 0) |
SET_BITS(bit_size == 64, 4, 4) |
SET_BITS(response_expected, 5, 5);
return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
return brw_dp_desc(devinfo, GFX8_BTI_STATELESS_NON_COHERENT,
msg_type, msg_control);
}
@ -924,14 +924,14 @@ brw_dp_a64_untyped_atomic_float_desc(const struct gen_device_info *devinfo,
assert(exec_size > 0);
const unsigned msg_type = bit_size == 32 ?
GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP :
GEN12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_FLOAT_OP;
GFX9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP :
GFX12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_FLOAT_OP;
const unsigned msg_control =
SET_BITS(atomic_op, 1, 0) |
SET_BITS(response_expected, 5, 5);
return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
return brw_dp_desc(devinfo, GFX8_BTI_STATELESS_NON_COHERENT,
msg_type, msg_control);
}
@ -955,7 +955,7 @@ brw_dp_typed_atomic_desc(const struct gen_device_info *devinfo,
} else {
/* SIMD4x2 typed surface R/W messages only exist on HSW+ */
assert(exec_size > 0);
msg_type = GEN7_DATAPORT_RC_TYPED_ATOMIC_OP;
msg_type = GFX7_DATAPORT_RC_TYPED_ATOMIC_OP;
}
const bool high_sample_mask = (exec_group / 8) % 2 == 1;
@ -986,13 +986,13 @@ brw_dp_typed_surface_rw_desc(const struct gen_device_info *devinfo,
if (devinfo->ver >= 8 || devinfo->is_haswell) {
msg_type = HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE;
} else {
msg_type = GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE;
msg_type = GFX7_DATAPORT_RC_TYPED_SURFACE_WRITE;
}
} else {
if (devinfo->ver >= 8 || devinfo->is_haswell) {
msg_type = HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ;
} else {
msg_type = GEN7_DATAPORT_RC_TYPED_SURFACE_READ;
msg_type = GFX7_DATAPORT_RC_TYPED_SURFACE_READ;
}
}

256
src/intel/compiler/brw_eu_defines.h
View file

@ -88,8 +88,8 @@
#define BRW_SPRITE_POINT_ENABLE 16
# define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT 0
# define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID 1
# define GFX7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT 0
# define GFX7_GS_CONTROL_DATA_FORMAT_GSCTL_SID 1
/* Execution Unit (EU) defines
*/
@ -111,12 +111,12 @@ enum brw_compression {
BRW_COMPRESSION_COMPRESSED = 2,
};
#define GEN6_COMPRESSION_1Q 0
#define GEN6_COMPRESSION_2Q 1
#define GEN6_COMPRESSION_3Q 2
#define GEN6_COMPRESSION_4Q 3
#define GEN6_COMPRESSION_1H 0
#define GEN6_COMPRESSION_2H 2
#define GFX6_COMPRESSION_1Q 0
#define GFX6_COMPRESSION_2Q 1
#define GFX6_COMPRESSION_3Q 2
#define GFX6_COMPRESSION_4Q 3
#define GFX6_COMPRESSION_1H 0
#define GFX6_COMPRESSION_2H 2
enum PACKED brw_conditional_mod {
BRW_CONDITIONAL_NONE = 0,
@ -466,7 +466,7 @@ enum opcode {
* Source 1: Immediate bool to indicate whether control is returned to the
* thread only after the fence has been honored.
* Source 2: Immediate byte indicating which memory to fence. Zero means
* global memory; GEN7_BTI_SLM means SLM (for Gen11+ only).
* global memory; GFX7_BTI_SLM means SLM (for Gen11+ only).
*
* Vec4 backend only uses Source 0.
*/
@ -872,7 +872,7 @@ enum fb_write_logical_srcs {
FB_WRITE_LOGICAL_SRC_COLOR1, /* for dual source blend messages */
FB_WRITE_LOGICAL_SRC_SRC0_ALPHA,
FB_WRITE_LOGICAL_SRC_SRC_DEPTH, /* gl_FragDepth */
FB_WRITE_LOGICAL_SRC_DST_DEPTH, /* GEN4-5: passthrough from thread */
FB_WRITE_LOGICAL_SRC_DST_DEPTH, /* GFX4-5: passthrough from thread */
FB_WRITE_LOGICAL_SRC_SRC_STENCIL, /* gl_FragStencilRefARB */
FB_WRITE_LOGICAL_SRC_OMASK, /* Sample Mask (gl_SampleMask) */
FB_WRITE_LOGICAL_SRC_COMPONENTS, /* REQUIRED */
@ -1235,12 +1235,12 @@ enum brw_message_target {
BRW_SFID_THREAD_SPAWNER = 7,
BRW_SFID_VME = 8,
GEN6_SFID_DATAPORT_SAMPLER_CACHE = 4,
GEN6_SFID_DATAPORT_RENDER_CACHE = 5,
GEN6_SFID_DATAPORT_CONSTANT_CACHE = 9,
GFX6_SFID_DATAPORT_SAMPLER_CACHE = 4,
GFX6_SFID_DATAPORT_RENDER_CACHE = 5,
GFX6_SFID_DATAPORT_CONSTANT_CACHE = 9,
GEN7_SFID_DATAPORT_DATA_CACHE = 10,
GEN7_SFID_PIXEL_INTERPOLATOR = 11,
GFX7_SFID_DATAPORT_DATA_CACHE = 10,
GFX7_SFID_PIXEL_INTERPOLATOR = 11,
HSW_SFID_DATAPORT_DATA_CACHE_1 = 12,
HSW_SFID_CRE = 13,
@ -1248,7 +1248,7 @@ enum brw_message_target {
GEN_RT_SFID_RAY_TRACE_ACCELERATOR = 8,
};
#define GEN7_MESSAGE_TARGET_DP_DATA_CACHE 10
#define GFX7_MESSAGE_TARGET_DP_DATA_CACHE 10
#define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0
#define BRW_SAMPLER_RETURN_FORMAT_UINT32 2
@ -1273,53 +1273,53 @@ enum brw_message_target {
#define BRW_SAMPLER_MESSAGE_SIMD8_LD 3
#define BRW_SAMPLER_MESSAGE_SIMD16_LD 3
#define GEN5_SAMPLER_MESSAGE_SAMPLE 0
#define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS 1
#define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD 2
#define GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE 3
#define GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS 4
#define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5
#define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE 6
#define GEN5_SAMPLER_MESSAGE_SAMPLE_LD 7
#define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4 8
#define GEN5_SAMPLER_MESSAGE_LOD 9
#define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO 10
#define GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO 11
#define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C 16
#define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO 17
#define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C 18
#define GFX5_SAMPLER_MESSAGE_SAMPLE 0
#define GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS 1
#define GFX5_SAMPLER_MESSAGE_SAMPLE_LOD 2
#define GFX5_SAMPLER_MESSAGE_SAMPLE_COMPARE 3
#define GFX5_SAMPLER_MESSAGE_SAMPLE_DERIVS 4
#define GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5
#define GFX5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE 6
#define GFX5_SAMPLER_MESSAGE_SAMPLE_LD 7
#define GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4 8
#define GFX5_SAMPLER_MESSAGE_LOD 9
#define GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO 10
#define GFX6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO 11
#define GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C 16
#define GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO 17
#define GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C 18
#define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20
#define GEN9_SAMPLER_MESSAGE_SAMPLE_LZ 24
#define GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ 25
#define GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ 26
#define GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W 28
#define GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS 29
#define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS 30
#define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS 31
#define GFX9_SAMPLER_MESSAGE_SAMPLE_LZ 24
#define GFX9_SAMPLER_MESSAGE_SAMPLE_C_LZ 25
#define GFX9_SAMPLER_MESSAGE_SAMPLE_LD_LZ 26
#define GFX9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W 28
#define GFX7_SAMPLER_MESSAGE_SAMPLE_LD_MCS 29
#define GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DMS 30
#define GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DSS 31
/* for GEN5 only */
/* for GFX5 only */
#define BRW_SAMPLER_SIMD_MODE_SIMD4X2 0
#define BRW_SAMPLER_SIMD_MODE_SIMD8 1
#define BRW_SAMPLER_SIMD_MODE_SIMD16 2
#define BRW_SAMPLER_SIMD_MODE_SIMD32_64 3
/* GEN9 changes SIMD mode 0 to mean SIMD8D, but lets us get the SIMD4x2
/* GFX9 changes SIMD mode 0 to mean SIMD8D, but lets us get the SIMD4x2
* behavior by setting bit 22 of dword 2 in the message header. */
#define GEN9_SAMPLER_SIMD_MODE_SIMD8D 0
#define GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2 (1 << 22)
#define GFX9_SAMPLER_SIMD_MODE_SIMD8D 0
#define GFX9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2 (1 << 22)
#define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0
#define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1
#define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS 2
#define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS 3
#define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS 4
#define GEN12_DATAPORT_OWORD_BLOCK_16_OWORDS 5
#define GFX12_DATAPORT_OWORD_BLOCK_16_OWORDS 5
#define BRW_DATAPORT_OWORD_BLOCK_OWORDS(n) \
((n) == 1 ? BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW : \
(n) == 2 ? BRW_DATAPORT_OWORD_BLOCK_2_OWORDS : \
(n) == 4 ? BRW_DATAPORT_OWORD_BLOCK_4_OWORDS : \
(n) == 8 ? BRW_DATAPORT_OWORD_BLOCK_8_OWORDS : \
(n) == 16 ? GEN12_DATAPORT_OWORD_BLOCK_16_OWORDS : \
(n) == 16 ? GFX12_DATAPORT_OWORD_BLOCK_16_OWORDS : \
(abort(), ~0))
#define BRW_DATAPORT_OWORD_BLOCK_DWORDS(n) \
((n) == 4 ? BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW : \
@ -1336,22 +1336,22 @@ enum brw_message_target {
/* This one stays the same across generations. */
#define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0
/* GEN4 */
/* GFX4 */
#define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1
#define BRW_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 2
#define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3
/* G45, GEN5 */
/* G45, GFX5 */
#define G45_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
#define G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
#define G45_DATAPORT_READ_MESSAGE_AVC_LOOP_FILTER_READ 3
#define G45_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
#define G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
/* GEN6 */
#define GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
#define GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
#define GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
#define GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ 5
#define GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
/* GFX6 */
#define GFX6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
#define GFX6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
#define GFX6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
#define GFX6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ 5
#define GFX6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
#define BRW_DATAPORT_READ_TARGET_DATA_CACHE 0
#define BRW_DATAPORT_READ_TARGET_RENDER_CACHE 1
@ -1371,48 +1371,48 @@ enum brw_message_target {
#define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5
#define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7
/* GEN6 */
#define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE 7
#define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 8
#define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 9
#define GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 10
#define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 11
#define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 12
#define GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE 13
#define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE 14
/* GFX6 */
#define GFX6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE 7
#define GFX6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 8
#define GFX6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 9
#define GFX6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 10
#define GFX6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 11
#define GFX6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 12
#define GFX6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE 13
#define GFX6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE 14
/* GEN7 */
#define GEN7_DATAPORT_RC_MEDIA_BLOCK_READ 4
#define GEN7_DATAPORT_RC_TYPED_SURFACE_READ 5
#define GEN7_DATAPORT_RC_TYPED_ATOMIC_OP 6
#define GEN7_DATAPORT_RC_MEMORY_FENCE 7
#define GEN7_DATAPORT_RC_MEDIA_BLOCK_WRITE 10
#define GEN7_DATAPORT_RC_RENDER_TARGET_WRITE 12
#define GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE 13
#define GEN7_DATAPORT_DC_OWORD_BLOCK_READ 0
#define GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ 1
#define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ 2
#define GEN7_DATAPORT_DC_DWORD_SCATTERED_READ 3
#define GEN7_DATAPORT_DC_BYTE_SCATTERED_READ 4
#define GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ 5
#define GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP 6
#define GEN7_DATAPORT_DC_MEMORY_FENCE 7
#define GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE 8
#define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE 10
#define GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE 11
#define GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE 12
#define GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE 13
/* GFX7 */
#define GFX7_DATAPORT_RC_MEDIA_BLOCK_READ 4
#define GFX7_DATAPORT_RC_TYPED_SURFACE_READ 5
#define GFX7_DATAPORT_RC_TYPED_ATOMIC_OP 6
#define GFX7_DATAPORT_RC_MEMORY_FENCE 7
#define GFX7_DATAPORT_RC_MEDIA_BLOCK_WRITE 10
#define GFX7_DATAPORT_RC_RENDER_TARGET_WRITE 12
#define GFX7_DATAPORT_RC_TYPED_SURFACE_WRITE 13
#define GFX7_DATAPORT_DC_OWORD_BLOCK_READ 0
#define GFX7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ 1
#define GFX7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ 2
#define GFX7_DATAPORT_DC_DWORD_SCATTERED_READ 3
#define GFX7_DATAPORT_DC_BYTE_SCATTERED_READ 4
#define GFX7_DATAPORT_DC_UNTYPED_SURFACE_READ 5
#define GFX7_DATAPORT_DC_UNTYPED_ATOMIC_OP 6
#define GFX7_DATAPORT_DC_MEMORY_FENCE 7
#define GFX7_DATAPORT_DC_OWORD_BLOCK_WRITE 8
#define GFX7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE 10
#define GFX7_DATAPORT_DC_DWORD_SCATTERED_WRITE 11
#define GFX7_DATAPORT_DC_BYTE_SCATTERED_WRITE 12
#define GFX7_DATAPORT_DC_UNTYPED_SURFACE_WRITE 13
#define GEN7_DATAPORT_SCRATCH_READ ((1 << 18) | \
#define GFX7_DATAPORT_SCRATCH_READ ((1 << 18) | \
(0 << 17))
#define GEN7_DATAPORT_SCRATCH_WRITE ((1 << 18) | \
#define GFX7_DATAPORT_SCRATCH_WRITE ((1 << 18) | \
(1 << 17))
#define GEN7_DATAPORT_SCRATCH_NUM_REGS_SHIFT 12
#define GFX7_DATAPORT_SCRATCH_NUM_REGS_SHIFT 12
#define GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET 0
#define GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE 1
#define GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID 2
#define GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET 3
#define GFX7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET 0
#define GFX7_PIXEL_INTERPOLATOR_LOC_SAMPLE 1
#define GFX7_PIXEL_INTERPOLATOR_LOC_CENTROID 2
#define GFX7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET 3
/* HSW */
#define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_READ 0
@ -1438,31 +1438,31 @@ enum brw_message_target {
#define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP 11
#define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2 12
#define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE 13
#define GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ 0x10
#define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ 0x11
#define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP 0x12
#define GEN12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_INT_OP 0x13
#define GEN9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_READ 0x14
#define GEN9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_WRITE 0x15
#define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE 0x19
#define GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE 0x1a
#define GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP 0x1b
#define GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP 0x1d
#define GEN12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_FLOAT_OP 0x1e
#define GFX9_DATAPORT_DC_PORT1_A64_SCATTERED_READ 0x10
#define GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ 0x11
#define GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP 0x12
#define GFX12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_INT_OP 0x13
#define GFX9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_READ 0x14
#define GFX9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_WRITE 0x15
#define GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE 0x19
#define GFX8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE 0x1a
#define GFX9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP 0x1b
#define GFX9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP 0x1d
#define GFX12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_FLOAT_OP 0x1e
/* GEN9 */
#define GEN9_DATAPORT_RC_RENDER_TARGET_WRITE 12
#define GEN9_DATAPORT_RC_RENDER_TARGET_READ 13
/* GFX9 */
#define GFX9_DATAPORT_RC_RENDER_TARGET_WRITE 12
#define GFX9_DATAPORT_RC_RENDER_TARGET_READ 13
/* A64 scattered message subtype */
#define GEN8_A64_SCATTERED_SUBTYPE_BYTE 0
#define GEN8_A64_SCATTERED_SUBTYPE_DWORD 1
#define GEN8_A64_SCATTERED_SUBTYPE_QWORD 2
#define GEN8_A64_SCATTERED_SUBTYPE_HWORD 3
#define GFX8_A64_SCATTERED_SUBTYPE_BYTE 0
#define GFX8_A64_SCATTERED_SUBTYPE_DWORD 1
#define GFX8_A64_SCATTERED_SUBTYPE_QWORD 2
#define GFX8_A64_SCATTERED_SUBTYPE_HWORD 3
/* Dataport special binding table indices: */
#define BRW_BTI_STATELESS 255
#define GEN7_BTI_SLM 254
#define GFX7_BTI_SLM 254
#define HSW_BTI_STATELESS_LOCALLY_COHERENT 255
#define HSW_BTI_STATELESS_NON_COHERENT 253
@ -1495,9 +1495,9 @@ enum brw_message_target {
* (matching the behavior of the same BTI on pre-Gen8 hardware) and BTI 255
* may actually be an alias for BTI 253.
*/
#define GEN8_BTI_STATELESS_IA_COHERENT 255
#define GEN8_BTI_STATELESS_NON_COHERENT 253
#define GEN9_BTI_BINDLESS 252
#define GFX8_BTI_STATELESS_IA_COHERENT 255
#define GFX8_BTI_STATELESS_NON_COHERENT 253
#define GFX9_BTI_BINDLESS 252
/* Dataport atomic operations for Untyped Atomic Integer Operation message
* (and others).
@ -1536,8 +1536,8 @@ enum brw_message_target {
#define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11
#define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12
#define BRW_MATH_FUNCTION_INT_DIV_REMAINDER 13
#define GEN8_MATH_FUNCTION_INVM 14
#define GEN8_MATH_FUNCTION_RSQRTM 15
#define GFX8_MATH_FUNCTION_INVM 14
#define GFX8_MATH_FUNCTION_RSQRTM 15
#define BRW_MATH_INTEGER_UNSIGNED 0
#define BRW_MATH_INTEGER_SIGNED 1
@ -1555,11 +1555,11 @@ enum brw_message_target {
#define BRW_URB_OPCODE_WRITE_OWORD 1
#define BRW_URB_OPCODE_READ_HWORD 2
#define BRW_URB_OPCODE_READ_OWORD 3
#define GEN7_URB_OPCODE_ATOMIC_MOV 4
#define GEN7_URB_OPCODE_ATOMIC_INC 5
#define GEN8_URB_OPCODE_ATOMIC_ADD 6
#define GEN8_URB_OPCODE_SIMD8_WRITE 7
#define GEN8_URB_OPCODE_SIMD8_READ 8
#define GFX7_URB_OPCODE_ATOMIC_MOV 4
#define GFX7_URB_OPCODE_ATOMIC_INC 5
#define GFX8_URB_OPCODE_ATOMIC_ADD 6
#define GFX8_URB_OPCODE_SIMD8_WRITE 7
#define GFX8_URB_OPCODE_SIMD8_READ 8
#define BRW_URB_SWIZZLE_NONE 0
#define BRW_URB_SWIZZLE_INTERLEAVE 1
@ -1592,15 +1592,15 @@ enum brw_message_target {
*
* Identical for VS, DS, and HS.
*/
#define GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES (512*64)
#define GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES (512*64)
#define GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES (512*64)
#define GEN7_MAX_VS_URB_ENTRY_SIZE_BYTES (512*64)
#define GFX7_MAX_GS_URB_ENTRY_SIZE_BYTES (512*64)
#define GFX7_MAX_DS_URB_ENTRY_SIZE_BYTES (512*64)
#define GFX7_MAX_HS_URB_ENTRY_SIZE_BYTES (512*64)
#define GFX7_MAX_VS_URB_ENTRY_SIZE_BYTES (512*64)
/* Gen6 "GS URB Entry Allocation Size" is defined as a number of 1024-bit
* (128 bytes) URB rows and the maximum allowed value is 5 rows.
*/
#define GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES (5*128)
#define GFX6_MAX_GS_URB_ENTRY_SIZE_BYTES (5*128)
/* GS Thread Payload
*/
@ -1608,11 +1608,11 @@ enum brw_message_target {
/* 3DSTATE_GS "Output Vertex Size" has an effective maximum of 62. It's
* counted in multiples of 16 bytes.
*/
#define GEN7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES (62*16)
#define GFX7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES (62*16)
/* R0 */
# define GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT 27
# define GFX7_GS_PAYLOAD_INSTANCE_ID_SHIFT 27
/* CR0.0[5:4] Floating-Point Rounding Modes
* Skylake PRM, Volume 7 Part 1, "Control Register", page 756
@ -1644,9 +1644,9 @@ enum PACKED brw_rnd_mode {
* Specifies the number of Bytes to be read or written per Dword used at
* byte_scattered read/write and byte_scaled read/write messages.
*/
#define GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE 0
#define GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD 1
#define GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD 2
#define GFX7_BYTE_SCATTERED_DATA_ELEMENT_BYTE 0
#define GFX7_BYTE_SCATTERED_DATA_ELEMENT_WORD 1
#define GFX7_BYTE_SCATTERED_DATA_ELEMENT_DWORD 2
#define GEN_RT_BTD_MESSAGE_SPAWN 1

50
src/intel/compiler/brw_eu_emit.c
View file

@ -81,7 +81,7 @@ gen7_convert_mrf_to_grf(struct brw_codegen *p, struct brw_reg *reg)
const struct gen_device_info *devinfo = p->devinfo;
if (devinfo->ver >= 7 && reg->file == BRW_MESSAGE_REGISTER_FILE) {
reg->file = BRW_GENERAL_REGISTER_FILE;
reg->nr += GEN7_MRF_HACK_START;
reg->nr += GFX7_MRF_HACK_START;
}
}
@ -600,7 +600,7 @@ gen7_set_dp_scratch_message(struct brw_codegen *p,
brw_set_desc(p, inst, brw_message_desc(
devinfo, mlen, rlen, header_present));
brw_inst_set_sfid(devinfo, inst, GEN7_SFID_DATAPORT_DATA_CACHE);
brw_inst_set_sfid(devinfo, inst, GFX7_SFID_DATAPORT_DATA_CACHE);
brw_inst_set_dp_category(devinfo, inst, 1); /* Scratch Block Read/Write msgs */
brw_inst_set_scratch_read_write(devinfo, inst, write);
brw_inst_set_scratch_type(devinfo, inst, dword);
@ -2114,7 +2114,7 @@ brw_scratch_surface_idx(const struct brw_codegen *p)
{
/* The scratch space is thread-local so IA coherency is unnecessary. */
if (p->devinfo->ver >= 8)
return GEN8_BTI_STATELESS_NON_COHERENT;
return GFX8_BTI_STATELESS_NON_COHERENT;
else
return BRW_BTI_STATELESS;
}
@ -2133,8 +2133,8 @@ void brw_oword_block_write_scratch(struct brw_codegen *p,
{
const struct gen_device_info *devinfo = p->devinfo;
const unsigned target_cache =
(devinfo->ver >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
devinfo->ver >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
(devinfo->ver >= 7 ? GFX7_SFID_DATAPORT_DATA_CACHE :
devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE :
BRW_SFID_DATAPORT_WRITE);
const struct tgl_swsb swsb = brw_get_default_swsb(p);
uint32_t msg_type;
@ -2216,7 +2216,7 @@ void brw_oword_block_write_scratch(struct brw_codegen *p,
}
if (devinfo->ver >= 6)
msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE;
msg_type = GFX6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE;
else
msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE;
@ -2266,8 +2266,8 @@ brw_oword_block_read_scratch(struct brw_codegen *p,
const unsigned rlen = num_regs;
const unsigned target_cache =
(devinfo->ver >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
devinfo->ver >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
(devinfo->ver >= 7 ? GFX7_SFID_DATAPORT_DATA_CACHE :
devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE :
BRW_SFID_DATAPORT_READ);
{
@ -2359,7 +2359,7 @@ void brw_oword_block_read(struct brw_codegen *p,
{
const struct gen_device_info *devinfo = p->devinfo;
const unsigned target_cache =
(devinfo->ver >= 6 ? GEN6_SFID_DATAPORT_CONSTANT_CACHE :
(devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_CONSTANT_CACHE :
BRW_SFID_DATAPORT_READ);
const unsigned exec_size = 1 << brw_get_default_exec_size(p);
const struct tgl_swsb swsb = brw_get_default_swsb(p);
@ -2431,7 +2431,7 @@ brw_fb_WRITE(struct brw_codegen *p,
{
const struct gen_device_info *devinfo = p->devinfo;
const unsigned target_cache =
(devinfo->ver >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
(devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE :
BRW_SFID_DATAPORT_WRITE);
brw_inst *insn;
unsigned msg_type;
@ -2454,7 +2454,7 @@ brw_fb_WRITE(struct brw_codegen *p,
/* headerless version, just submit color payload */
src0 = payload;
msg_type = GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE;
msg_type = GFX6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE;
} else {
assert(payload.file == BRW_MESSAGE_REGISTER_FILE);
brw_inst_set_base_mrf(devinfo, insn, payload.nr);
@ -2491,7 +2491,7 @@ gen9_fb_READ(struct brw_codegen *p,
brw_get_default_exec_size(p) == BRW_EXECUTE_16 ? 0 : 1;
brw_inst *insn = next_insn(p, BRW_OPCODE_SENDC);
brw_inst_set_sfid(devinfo, insn, GEN6_SFID_DATAPORT_RENDER_CACHE);
brw_inst_set_sfid(devinfo, insn, GFX6_SFID_DATAPORT_RENDER_CACHE);
brw_set_dest(p, insn, dst);
brw_set_src0(p, insn, payload);
brw_set_desc(
@ -2499,7 +2499,7 @@ gen9_fb_READ(struct brw_codegen *p,
brw_message_desc(devinfo, msg_length, response_length, true) |
brw_dp_read_desc(devinfo, binding_table_index,
per_sample << 5 | msg_subtype,
GEN9_DATAPORT_RC_RENDER_TARGET_READ,
GFX9_DATAPORT_RC_RENDER_TARGET_READ,
BRW_DATAPORT_READ_TARGET_RENDER_CACHE));
brw_inst_set_rt_slot_group(devinfo, insn, brw_get_default_group(p) / 16);
@ -3077,8 +3077,8 @@ brw_svb_write(struct brw_codegen *p,
{
const struct gen_device_info *devinfo = p->devinfo;
const unsigned target_cache =
(devinfo->ver >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
devinfo->ver >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
(devinfo->ver >= 7 ? GFX7_SFID_DATAPORT_DATA_CACHE :
devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE :
BRW_SFID_DATAPORT_WRITE);
brw_inst *insn;
@ -3092,7 +3092,7 @@ brw_svb_write(struct brw_codegen *p,
brw_message_desc(devinfo, 1, send_commit_msg, true) |
brw_dp_write_desc(devinfo, binding_table_index,
0, /* msg_control: ignored */
GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE,
GFX6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE,
0, /* last_render_target: ignored */
send_commit_msg)); /* send_commit_msg */
}
@ -3122,7 +3122,7 @@ brw_untyped_atomic(struct brw_codegen *p,
const struct gen_device_info *devinfo = p->devinfo;
const unsigned sfid = (devinfo->ver >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN7_SFID_DATAPORT_DATA_CACHE);
GFX7_SFID_DATAPORT_DATA_CACHE);
const bool align1 = brw_get_default_access_mode(p) == BRW_ALIGN_1;
/* SIMD4x2 untyped atomic instructions only exist on HSW+ */
const bool has_simd4x2 = devinfo->ver >= 8 || devinfo->is_haswell;
@ -3157,7 +3157,7 @@ brw_untyped_surface_read(struct brw_codegen *p,
const struct gen_device_info *devinfo = p->devinfo;
const unsigned sfid = (devinfo->ver >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN7_SFID_DATAPORT_DATA_CACHE);
GFX7_SFID_DATAPORT_DATA_CACHE);
const bool align1 = brw_get_default_access_mode(p) == BRW_ALIGN_1;
const unsigned exec_size = align1 ? 1 << brw_get_default_exec_size(p) : 0;
const unsigned response_length =
@ -3180,7 +3180,7 @@ brw_untyped_surface_write(struct brw_codegen *p,
const struct gen_device_info *devinfo = p->devinfo;
const unsigned sfid = (devinfo->ver >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN7_SFID_DATAPORT_DATA_CACHE);
GFX7_SFID_DATAPORT_DATA_CACHE);
const bool align1 = brw_get_default_access_mode(p) == BRW_ALIGN_1;
/* SIMD4x2 untyped surface write instructions only exist on HSW+ */
const bool has_simd4x2 = devinfo->ver >= 8 || devinfo->is_haswell;
@ -3211,11 +3211,11 @@ brw_set_memory_fence_message(struct brw_codegen *p,
brw_inst_set_sfid(devinfo, insn, sfid);
switch (sfid) {
case GEN6_SFID_DATAPORT_RENDER_CACHE:
brw_inst_set_dp_msg_type(devinfo, insn, GEN7_DATAPORT_RC_MEMORY_FENCE);
case GFX6_SFID_DATAPORT_RENDER_CACHE:
brw_inst_set_dp_msg_type(devinfo, insn, GFX7_DATAPORT_RC_MEMORY_FENCE);
break;
case GEN7_SFID_DATAPORT_DATA_CACHE:
brw_inst_set_dp_msg_type(devinfo, insn, GEN7_DATAPORT_DC_MEMORY_FENCE);
case GFX7_SFID_DATAPORT_DATA_CACHE:
brw_inst_set_dp_msg_type(devinfo, insn, GFX7_DATAPORT_DC_MEMORY_FENCE);
break;
default:
unreachable("Not reached");
@ -3276,7 +3276,7 @@ brw_pixel_interpolator_query(struct brw_codegen *p,
* if data is actually immediate.
*/
brw_send_indirect_message(p,
GEN7_SFID_PIXEL_INTERPOLATOR,
GFX7_SFID_PIXEL_INTERPOLATOR,
dest,
mrf,
vec1(data),
@ -3564,7 +3564,7 @@ void brw_shader_time_add(struct brw_codegen *p,
const struct gen_device_info *devinfo = p->devinfo;
const unsigned sfid = (devinfo->ver >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN7_SFID_DATAPORT_DATA_CACHE);
GFX7_SFID_DATAPORT_DATA_CACHE);
assert(devinfo->ver >= 7);
brw_push_insn_state(p);

4
src/intel/compiler/brw_eu_validate.c
View file

@ -254,8 +254,8 @@ num_sources_from_inst(const struct gen_device_info *devinfo,
case BRW_MATH_FUNCTION_SIN:
case BRW_MATH_FUNCTION_COS:
case BRW_MATH_FUNCTION_SINCOS:
case GEN8_MATH_FUNCTION_INVM:
case GEN8_MATH_FUNCTION_RSQRTM:
case GFX8_MATH_FUNCTION_INVM:
case GFX8_MATH_FUNCTION_RSQRTM:
return 1;
case BRW_MATH_FUNCTION_FDIV:
case BRW_MATH_FUNCTION_POW:

84
src/intel/compiler/brw_fs.cpp
View file

@ -1675,9 +1675,9 @@ fs_visitor::assign_curb_setup()
fs_inst *send = ubld.group(send_width, 0).emit(SHADER_OPCODE_SEND,
dest, srcs, 4);
send->sfid = GEN7_SFID_DATAPORT_DATA_CACHE;
send->desc = brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
GEN7_DATAPORT_DC_OWORD_BLOCK_READ,
send->sfid = GFX7_SFID_DATAPORT_DATA_CACHE;
send->desc = brw_dp_desc(devinfo, GFX8_BTI_STATELESS_NON_COHERENT,
GFX7_DATAPORT_DC_OWORD_BLOCK_READ,
BRW_DATAPORT_OWORD_BLOCK_OWORDS(num_regs * 2));
send->header_size = 1;
send->mlen = 1;
@ -4660,7 +4660,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
inst->desc =
(inst->group / 16) << 11 | /* rt slot group */
brw_dp_write_desc(devinfo, inst->target, msg_ctl,
GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE,
GFX6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE,
inst->last_rt, false);
uint32_t ex_desc = 0;
@ -4677,7 +4677,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
inst->opcode = SHADER_OPCODE_SEND;
inst->resize_sources(3);
inst->sfid = GEN6_SFID_DATAPORT_RENDER_CACHE;
inst->sfid = GFX6_SFID_DATAPORT_RENDER_CACHE;
inst->src[0] = brw_imm_ud(0);
inst->src[1] = brw_imm_ud(0);
inst->src[2] = payload;
@ -4971,54 +4971,54 @@ sampler_msg_type(const gen_device_info *devinfo,
assert(devinfo->ver >= 5);
switch (opcode) {
case SHADER_OPCODE_TEX:
return shadow_compare ? GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE :
GEN5_SAMPLER_MESSAGE_SAMPLE;
return shadow_compare ? GFX5_SAMPLER_MESSAGE_SAMPLE_COMPARE :
GFX5_SAMPLER_MESSAGE_SAMPLE;
case FS_OPCODE_TXB:
return shadow_compare ? GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE :
GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
return shadow_compare ? GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE :
GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS;
case SHADER_OPCODE_TXL:
return shadow_compare ? GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE :
GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
return shadow_compare ? GFX5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE :
GFX5_SAMPLER_MESSAGE_SAMPLE_LOD;
case SHADER_OPCODE_TXL_LZ:
return shadow_compare ? GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ :
GEN9_SAMPLER_MESSAGE_SAMPLE_LZ;
return shadow_compare ? GFX9_SAMPLER_MESSAGE_SAMPLE_C_LZ :
GFX9_SAMPLER_MESSAGE_SAMPLE_LZ;
case SHADER_OPCODE_TXS:
case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
return GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
return GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
case SHADER_OPCODE_TXD:
assert(!shadow_compare || devinfo->ver >= 8 || devinfo->is_haswell);
return shadow_compare ? HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE :
GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
GFX5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
case SHADER_OPCODE_TXF:
return GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
return GFX5_SAMPLER_MESSAGE_SAMPLE_LD;
case SHADER_OPCODE_TXF_LZ:
assert(devinfo->ver >= 9);
return GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ;
return GFX9_SAMPLER_MESSAGE_SAMPLE_LD_LZ;
case SHADER_OPCODE_TXF_CMS_W:
assert(devinfo->ver >= 9);
return GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
return GFX9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
case SHADER_OPCODE_TXF_CMS:
return devinfo->ver >= 7 ? GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS :
GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
return devinfo->ver >= 7 ? GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DMS :
GFX5_SAMPLER_MESSAGE_SAMPLE_LD;
case SHADER_OPCODE_TXF_UMS:
assert(devinfo->ver >= 7);
return GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
return GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
case SHADER_OPCODE_TXF_MCS:
assert(devinfo->ver >= 7);
return GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
return GFX7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
case SHADER_OPCODE_LOD:
return GEN5_SAMPLER_MESSAGE_LOD;
return GFX5_SAMPLER_MESSAGE_LOD;
case SHADER_OPCODE_TG4:
assert(devinfo->ver >= 7);
return shadow_compare ? GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C :
GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
return shadow_compare ? GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C :
GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
break;
case SHADER_OPCODE_TG4_OFFSET:
assert(devinfo->ver >= 7);
return shadow_compare ? GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C :
GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
return shadow_compare ? GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C :
GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
case SHADER_OPCODE_SAMPLEINFO:
return GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
return GFX6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
default:
unreachable("not reached");
}
@ -5343,7 +5343,7 @@ lower_sampler_logical_send_gen7(const fs_builder &bld, fs_inst *inst, opcode op,
/* Bindless surface */
assert(devinfo->ver >= 9);
inst->desc = brw_sampler_desc(devinfo,
GEN9_BTI_BINDLESS,
GFX9_BTI_BINDLESS,
sampler.file == IMM ? sampler.ud % 16 : 0,
msg_type,
simd_mode,
@ -5510,7 +5510,7 @@ setup_surface_descriptors(const fs_builder &bld, fs_inst *inst, uint32_t desc,
} else if (surface_handle.file != BAD_FILE) {
/* Bindless surface */
assert(devinfo->ver >= 9);
inst->desc = desc | GEN9_BTI_BINDLESS;
inst->desc = desc | GFX9_BTI_BINDLESS;
inst->src[0] = brw_imm_ud(0);
/* We assume that the driver provided the handle in the top 20 bits so
@ -5560,7 +5560,7 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst)
const bool is_stateless =
surface.file == IMM && (surface.ud == BRW_BTI_STATELESS ||
surface.ud == GEN8_BTI_STATELESS_NON_COHERENT);
surface.ud == GFX8_BTI_STATELESS_NON_COHERENT);
const bool has_side_effects = inst->has_side_effects();
@ -5646,13 +5646,13 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst)
case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
/* Byte scattered opcodes go through the normal data cache */
sfid = GEN7_SFID_DATAPORT_DATA_CACHE;
sfid = GFX7_SFID_DATAPORT_DATA_CACHE;
break;
case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL:
case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL:
sfid = devinfo->ver >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
devinfo->ver >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
sfid = devinfo->ver >= 7 ? GFX7_SFID_DATAPORT_DATA_CACHE :
devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE :
BRW_DATAPORT_READ_TARGET_RENDER_CACHE;
break;
@ -5665,7 +5665,7 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst)
*/
sfid = (devinfo->ver >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN7_SFID_DATAPORT_DATA_CACHE);
GFX7_SFID_DATAPORT_DATA_CACHE);
break;
case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
@ -5676,7 +5676,7 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst)
*/
sfid = (devinfo->ver >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN6_SFID_DATAPORT_RENDER_CACHE);
GFX6_SFID_DATAPORT_RENDER_CACHE);
break;
default:
@ -5792,7 +5792,7 @@ lower_surface_block_logical_send(const fs_builder &bld, fs_inst *inst)
const bool is_stateless =
surface.file == IMM && (surface.ud == BRW_BTI_STATELESS ||
surface.ud == GEN8_BTI_STATELESS_NON_COHERENT);
surface.ud == GFX8_BTI_STATELESS_NON_COHERENT);
const bool has_side_effects = inst->has_side_effects();
@ -5831,7 +5831,7 @@ lower_surface_block_logical_send(const fs_builder &bld, fs_inst *inst)
inst->send_has_side_effects = has_side_effects;
inst->send_is_volatile = !has_side_effects;
inst->sfid = GEN7_SFID_DATAPORT_DATA_CACHE;
inst->sfid = GFX7_SFID_DATAPORT_DATA_CACHE;
const uint32_t desc = brw_dp_oword_block_rw_desc(devinfo, align_16B,
arg.ud, write);
@ -6061,17 +6061,17 @@ lower_varying_pull_constant_logical_send(const fs_builder &bld, fs_inst *inst)
inst->sfid = BRW_SFID_SAMPLER;
inst->desc |= brw_sampler_desc(devinfo, 0, 0,
GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
GFX5_SAMPLER_MESSAGE_SAMPLE_LD,
simd_mode, 0);
} else if (alignment >= 4) {
inst->sfid = (devinfo->ver >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN7_SFID_DATAPORT_DATA_CACHE);
GFX7_SFID_DATAPORT_DATA_CACHE);
inst->desc |= brw_dp_untyped_surface_rw_desc(devinfo, inst->exec_size,
4, /* num_channels */
false /* write */);
} else {
inst->sfid = GEN7_SFID_DATAPORT_DATA_CACHE;
inst->sfid = GFX7_SFID_DATAPORT_DATA_CACHE;
inst->desc |= brw_dp_byte_scattered_rw_desc(devinfo, inst->exec_size,
32, /* bit_size */
false /* write */);
@ -7706,7 +7706,7 @@ fs_visitor::setup_fs_payload_gen6()
payload.num_regs += payload_width / 8;
}
/* R29-30: interpolated W set if GEN6_WM_USES_SOURCE_W. */
/* R29-30: interpolated W set if GFX6_WM_USES_SOURCE_W. */
if (prog_data->uses_src_w) {
payload.source_w_reg[j] = payload.num_regs;
payload.num_regs += payload_width / 8;

2
src/intel/compiler/brw_fs.h
View file

@ -379,7 +379,7 @@ public:
fs_reg outputs[VARYING_SLOT_MAX];
fs_reg dual_src_output;
int first_non_payload_grf;
/** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
/** Either BRW_MAX_GRF or GFX7_MRF_HACK_START */
unsigned max_grf;
fs_reg *nir_locals;

2
src/intel/compiler/brw_fs_bank_conflicts.cpp
View file

@ -582,7 +582,7 @@ namespace {
assert(inst->dst.file != MRF);
for (unsigned i = 0; i < inst->implied_mrf_writes(); i++) {
const unsigned reg = GEN7_MRF_HACK_START + inst->base_mrf + i;
const unsigned reg = GFX7_MRF_HACK_START + inst->base_mrf + i;
constrained[p.atom_of_reg(reg)] = true;
}
}

50
src/intel/compiler/brw_fs_generator.cpp
View file

@ -838,7 +838,7 @@ fs_generator::generate_urb_read(fs_inst *inst,
brw_set_src1(p, send, brw_imm_ud(0u));
brw_inst_set_sfid(p->devinfo, send, BRW_SFID_URB);
brw_inst_set_urb_opcode(p->devinfo, send, GEN8_URB_OPCODE_SIMD8_READ);
brw_inst_set_urb_opcode(p->devinfo, send, GFX8_URB_OPCODE_SIMD8_READ);
if (inst->opcode == SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT)
brw_inst_set_urb_per_slot_offset(p->devinfo, send, true);
@ -860,7 +860,7 @@ fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
brw_set_src1(p, insn, brw_imm_ud(0u));
brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
brw_inst_set_urb_opcode(p->devinfo, insn, GFX8_URB_OPCODE_SIMD8_WRITE);
if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT ||
inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
@ -1064,7 +1064,7 @@ fs_generator::generate_get_buffer_size(fs_inst *inst,
src,
surf_index.ud,
0,
GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
rlen, /* response length */
inst->mlen,
inst->header_size > 0,
@ -1126,48 +1126,48 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst,
switch (inst->opcode) {
case SHADER_OPCODE_TEX:
if (inst->shadow_compare) {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
} else {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE;
}
break;
case FS_OPCODE_TXB:
if (inst->shadow_compare) {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
} else {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS;
}
break;
case SHADER_OPCODE_TXL:
if (inst->shadow_compare) {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
} else {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LOD;
}
break;
case SHADER_OPCODE_TXS:
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
break;
case SHADER_OPCODE_TXD:
assert(!inst->shadow_compare);
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
break;
case SHADER_OPCODE_TXF:
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LD;
break;
case SHADER_OPCODE_TXF_CMS:
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LD;
break;
case SHADER_OPCODE_LOD:
msg_type = GEN5_SAMPLER_MESSAGE_LOD;
msg_type = GFX5_SAMPLER_MESSAGE_LOD;
break;
case SHADER_OPCODE_TG4:
assert(devinfo->ver == 6);
assert(!inst->shadow_compare);
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
break;
case SHADER_OPCODE_SAMPLEINFO:
msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
msg_type = GFX6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
break;
default:
unreachable("not reached");
@ -1642,7 +1642,7 @@ fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
brw_pop_insn_state(p);
brw_inst_set_sfid(devinfo, send, GEN6_SFID_DATAPORT_CONSTANT_CACHE);
brw_inst_set_sfid(devinfo, send, GFX6_SFID_DATAPORT_CONSTANT_CACHE);
brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UD));
brw_set_src0(p, send, retype(payload, BRW_REGISTER_TYPE_UD));
brw_set_desc(p, send,
@ -1650,7 +1650,7 @@ fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
REG_SIZE), true) |
brw_dp_read_desc(devinfo, surf_index,
BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst->exec_size),
GEN7_DATAPORT_DC_OWORD_BLOCK_READ,
GFX7_DATAPORT_DC_OWORD_BLOCK_READ,
BRW_DATAPORT_READ_TARGET_DATA_CACHE));
} else {
@ -1671,14 +1671,14 @@ fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
/* dst = send(payload, a0.0 | <descriptor>) */
brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1));
brw_send_indirect_message(
p, GEN6_SFID_DATAPORT_CONSTANT_CACHE,
p, GFX6_SFID_DATAPORT_CONSTANT_CACHE,
retype(dst, BRW_REGISTER_TYPE_UD),
retype(payload, BRW_REGISTER_TYPE_UD), addr,
brw_message_desc(devinfo, 1,
DIV_ROUND_UP(inst->size_written, REG_SIZE), true) |
brw_dp_read_desc(devinfo, 0 /* surface */,
BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst->exec_size),
GEN7_DATAPORT_DC_OWORD_BLOCK_READ,
GFX7_DATAPORT_DC_OWORD_BLOCK_READ,
BRW_DATAPORT_READ_TARGET_DATA_CACHE),
false /* EOT */);
@ -1710,7 +1710,7 @@ fs_generator::generate_varying_pull_constant_load_gen4(fs_inst *inst,
}
if (devinfo->ver >= 5)
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LD;
else {
/* We always use the SIMD16 message so that we only have to load U, and
* not V or R.
@ -2293,7 +2293,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
generate_send(inst, dst, src[0], src[1], src[2],
inst->ex_mlen > 0 ? src[3] : brw_null_reg());
if ((inst->desc & 0xff) == BRW_BTI_STATELESS ||
(inst->desc & 0xff) == GEN8_BTI_STATELESS_NON_COHERENT) {
(inst->desc & 0xff) == GFX8_BTI_STATELESS_NON_COHERENT) {
if (inst->size_written)
fill_count++;
else
@ -2583,19 +2583,19 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
generate_pixel_interpolator_query(inst, dst, src[0], src[1],
GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
GFX7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
send_count++;
break;
case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
generate_pixel_interpolator_query(inst, dst, src[0], src[1],
GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
GFX7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
send_count++;
break;
case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
generate_pixel_interpolator_query(inst, dst, src[0], src[1],
GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
GFX7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
send_count++;
break;

28
src/intel/compiler/brw_fs_nir.cpp
View file

@ -2055,7 +2055,7 @@ fs_visitor::emit_gs_end_primitive(const nir_src &vertex_count_nir_src)
* output type is points, in which case EndPrimitive() is a no-op.
*/
if (gs_prog_data->control_data_format !=
GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT) {
GFX7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT) {
return;
}
@ -2346,7 +2346,7 @@ fs_visitor::emit_gs_vertex(const nir_src &vertex_count_nir_src,
*/
if (gs_compile->control_data_header_size_bits > 0 &&
gs_prog_data->control_data_format ==
GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID) {
GFX7_GS_CONTROL_DATA_FORMAT_GSCTL_SID) {
set_gs_stream_control_data_bits(vertex_count, stream_id);
}
}
@ -3738,7 +3738,7 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld,
const unsigned bit_size = nir_dest_bit_size(instr->dest);
fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GEN7_BTI_SLM);
srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GFX7_BTI_SLM);
srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[0]);
srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = brw_imm_ud(0);
@ -3775,7 +3775,7 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld,
const unsigned bit_size = nir_src_bit_size(instr->src[0]);
fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GEN7_BTI_SLM);
srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GFX7_BTI_SLM);
srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[1]);
srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = brw_imm_ud(1);
@ -4358,7 +4358,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
brw_vec8_grf(0, 0),
brw_imm_ud(commit_enable),
brw_imm_ud(/* bti */ 0));
fence->sfid = GEN7_SFID_DATAPORT_DATA_CACHE;
fence->sfid = GFX7_SFID_DATAPORT_DATA_CACHE;
fence_regs[fence_regs_count++] = fence->dst;
@ -4369,7 +4369,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
brw_vec8_grf(0, 0),
brw_imm_ud(commit_enable),
brw_imm_ud(/* bti */ 0));
render_fence->sfid = GEN6_SFID_DATAPORT_RENDER_CACHE;
render_fence->sfid = GFX6_SFID_DATAPORT_RENDER_CACHE;
fence_regs[fence_regs_count++] = render_fence->dst;
}
@ -4382,8 +4382,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
ubld.vgrf(BRW_REGISTER_TYPE_UD),
brw_vec8_grf(0, 0),
brw_imm_ud(commit_enable),
brw_imm_ud(GEN7_BTI_SLM));
fence->sfid = GEN7_SFID_DATAPORT_DATA_CACHE;
brw_imm_ud(GFX7_BTI_SLM));
fence->sfid = GFX7_SFID_DATAPORT_DATA_CACHE;
fence_regs[fence_regs_count++] = fence->dst;
}
@ -4895,7 +4895,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
if (devinfo->ver >= 8) {
srcs[SURFACE_LOGICAL_SRC_SURFACE] =
brw_imm_ud(GEN8_BTI_STATELESS_NON_COHERENT);
brw_imm_ud(GFX8_BTI_STATELESS_NON_COHERENT);
} else {
srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(BRW_BTI_STATELESS);
}
@ -4941,7 +4941,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
if (devinfo->ver >= 8) {
srcs[SURFACE_LOGICAL_SRC_SURFACE] =
brw_imm_ud(GEN8_BTI_STATELESS_NON_COHERENT);
brw_imm_ud(GFX8_BTI_STATELESS_NON_COHERENT);
} else {
srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(BRW_BTI_STATELESS);
}
@ -5418,7 +5418,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
srcs[SURFACE_LOGICAL_SRC_SURFACE] = is_ssbo ?
get_nir_ssbo_intrinsic_index(bld, instr) : fs_reg(brw_imm_ud(GEN7_BTI_SLM));
get_nir_ssbo_intrinsic_index(bld, instr) : fs_reg(brw_imm_ud(GFX7_BTI_SLM));
srcs[SURFACE_LOGICAL_SRC_ADDRESS] = address;
const fs_builder ubld1 = bld.exec_all().group(1, 0);
@ -5460,7 +5460,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
srcs[SURFACE_LOGICAL_SRC_SURFACE] = is_ssbo ?
get_nir_ssbo_intrinsic_index(bld, instr) : fs_reg(brw_imm_ud(GEN7_BTI_SLM));
get_nir_ssbo_intrinsic_index(bld, instr) : fs_reg(brw_imm_ud(GFX7_BTI_SLM));
srcs[SURFACE_LOGICAL_SRC_ADDRESS] = address;
const fs_builder ubld1 = bld.exec_all().group(1, 0);
@ -5613,7 +5613,7 @@ fs_visitor::nir_emit_shared_atomic(const fs_builder &bld,
dest = get_nir_dest(instr->dest);
fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GEN7_BTI_SLM);
srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GFX7_BTI_SLM);
srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(op);
srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = brw_imm_ud(1);
@ -5655,7 +5655,7 @@ fs_visitor::nir_emit_shared_atomic_float(const fs_builder &bld,
dest = get_nir_dest(instr->dest);
fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GEN7_BTI_SLM);
srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GFX7_BTI_SLM);
srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(op);
srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = brw_imm_ud(1);

14
src/intel/compiler/brw_fs_reg_allocate.cpp
View file

@ -771,7 +771,7 @@ fs_reg_alloc::build_interference_graph(bool allow_spilling)
node_count += payload_node_count;
if (devinfo->ver >= 7 && devinfo->ver < 9 && allow_spilling) {
first_mrf_hack_node = node_count;
node_count += BRW_MAX_GRF - GEN7_MRF_HACK_START;
node_count += BRW_MAX_GRF - GFX7_MRF_HACK_START;
} else {
first_mrf_hack_node = -1;
}
@ -826,7 +826,7 @@ fs_reg_alloc::build_interference_graph(bool allow_spilling)
*/
for (int i = 0; i < BRW_MAX_MRF(devinfo->ver); i++) {
ra_set_node_reg(g, first_mrf_hack_node + i,
GEN7_MRF_HACK_START + i);
GFX7_MRF_HACK_START + i);
}
}
@ -907,9 +907,9 @@ fs_reg_alloc::emit_unspill(const fs_builder &bld, fs_reg dst,
unspill_inst->size_written = reg_size * REG_SIZE;
unspill_inst->send_has_side_effects = false;
unspill_inst->send_is_volatile = true;
unspill_inst->sfid = GEN7_SFID_DATAPORT_DATA_CACHE;
unspill_inst->sfid = GFX7_SFID_DATAPORT_DATA_CACHE;
unspill_inst->desc =
brw_dp_read_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
brw_dp_read_desc(devinfo, GFX8_BTI_STATELESS_NON_COHERENT,
BRW_DATAPORT_OWORD_BLOCK_DWORDS(reg_size * 8),
BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ,
BRW_DATAPORT_READ_TARGET_RENDER_CACHE);
@ -964,11 +964,11 @@ fs_reg_alloc::emit_spill(const fs_builder &bld, fs_reg src,
spill_inst->header_size = 1;
spill_inst->send_has_side_effects = true;
spill_inst->send_is_volatile = false;
spill_inst->sfid = GEN7_SFID_DATAPORT_DATA_CACHE;
spill_inst->sfid = GFX7_SFID_DATAPORT_DATA_CACHE;
spill_inst->desc =
brw_dp_write_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
brw_dp_write_desc(devinfo, GFX8_BTI_STATELESS_NON_COHERENT,
BRW_DATAPORT_OWORD_BLOCK_DWORDS(reg_size * 8),
GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE,
GFX6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE,
0 /* not a render target */,
false /* send_commit_msg */);
} else {

2
src/intel/compiler/brw_fs_scoreboard.cpp
View file

@ -585,7 +585,7 @@ namespace {
reg_offset(r) / REG_SIZE);
return (r.file == VGRF || r.file == FIXED_GRF ? &grf_deps[reg] :
r.file == MRF ? &grf_deps[GEN7_MRF_HACK_START + reg] :
r.file == MRF ? &grf_deps[GFX7_MRF_HACK_START + reg] :
r.file == ARF && reg >= BRW_ARF_ADDRESS &&
reg < BRW_ARF_ACCUMULATOR ? &addr_dep :
r.file == ARF && reg >= BRW_ARF_ACCUMULATOR &&

2
src/intel/compiler/brw_fs_visitor.cpp
View file

@ -959,7 +959,7 @@ fs_visitor::init()
this->source_depth_to_render_target = false;
this->runtime_check_aads_emit = false;
this->first_non_payload_grf = 0;
this->max_grf = devinfo->ver >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
this->max_grf = devinfo->ver >= 7 ? GFX7_MRF_HACK_START : BRW_MAX_GRF;
this->uniforms = 0;
this->last_scratch = 0;

46
src/intel/compiler/brw_gen_enum.h
View file

@ -25,18 +25,18 @@
#include "dev/gen_device_info.h"
enum gen {
GEN4 = (1 << 0),
GEN45 = (1 << 1),
GEN5 = (1 << 2),
GEN6 = (1 << 3),
GEN7 = (1 << 4),
GEN75 = (1 << 5),
GEN8 = (1 << 6),
GEN9 = (1 << 7),
GEN10 = (1 << 8),
GEN11 = (1 << 9),
GEN12 = (1 << 10),
GEN125 = (1 << 11),
GFX4 = (1 << 0),
GFX45 = (1 << 1),
GFX5 = (1 << 2),
GFX6 = (1 << 3),
GFX7 = (1 << 4),
GFX75 = (1 << 5),
GFX8 = (1 << 6),
GFX9 = (1 << 7),
GFX10 = (1 << 8),
GFX11 = (1 << 9),
GFX12 = (1 << 10),
GFX125 = (1 << 11),
GEN_ALL = ~0
};
@ -48,17 +48,17 @@ static enum gen
gen_from_devinfo(const struct gen_device_info *devinfo)
{
switch (devinfo->verx10) {
case 40: return GEN4;
case 45: return GEN45;
case 50: return GEN5;
case 60: return GEN6;
case 70: return GEN7;
case 75: return GEN75;
case 80: return GEN8;
case 90: return GEN9;
case 110: return GEN11;
case 120: return GEN12;
case 125: return GEN125;
case 40: return GFX4;
case 45: return GFX45;
case 50: return GFX5;
case 60: return GFX6;
case 70: return GFX7;
case 75: return GFX75;
case 80: return GFX8;
case 90: return GFX9;
case 110: return GFX11;
case 120: return GFX12;
case 125: return GFX125;
default:
unreachable("not reached");
}

14
src/intel/compiler/brw_ir_performance.cpp
View file

@ -929,14 +929,14 @@ namespace {
case SHADER_OPCODE_MEMORY_FENCE:
case SHADER_OPCODE_INTERLOCK:
switch (info.sfid) {
case GEN6_SFID_DATAPORT_RENDER_CACHE:
case GFX6_SFID_DATAPORT_RENDER_CACHE:
if (devinfo->ver >= 7)
return calculate_desc(info, unit_dp_rc, 2, 0, 0, 30 /* XXX */, 0,
10 /* XXX */, 300 /* XXX */, 0, 0, 0, 0);
else
abort();
case GEN7_SFID_DATAPORT_DATA_CACHE:
case GFX7_SFID_DATAPORT_DATA_CACHE:
case HSW_SFID_DATAPORT_DATA_CACHE_1:
if (devinfo->ver >= 7)
return calculate_desc(info, unit_dp_dc, 2, 0, 0, 30 /* XXX */, 0,
@ -1024,10 +1024,10 @@ namespace {
case SHADER_OPCODE_SEND:
switch (info.sfid) {
case GEN6_SFID_DATAPORT_RENDER_CACHE:
case GFX6_SFID_DATAPORT_RENDER_CACHE:
if (devinfo->ver >= 7) {
switch (brw_dp_desc_msg_type(devinfo, info.desc)) {
case GEN7_DATAPORT_RC_TYPED_ATOMIC_OP:
case GFX7_DATAPORT_RC_TYPED_ATOMIC_OP:
return calculate_desc(info, unit_dp_rc, 2, 0, 0,
30 /* XXX */, 450 /* XXX */,
10 /* XXX */, 100 /* XXX */,
@ -1052,7 +1052,7 @@ namespace {
else
abort();
}
case GEN7_SFID_DATAPORT_DATA_CACHE:
case GFX7_SFID_DATAPORT_DATA_CACHE:
case HSW_SFID_DATAPORT_DATA_CACHE_1:
if (devinfo->ver >= 8 || devinfo->is_haswell) {
switch (brw_dp_desc_msg_type(devinfo, info.desc)) {
@ -1073,7 +1073,7 @@ namespace {
}
} else if (devinfo->ver >= 7) {
switch (brw_dp_desc_msg_type(devinfo, info.desc)) {
case GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP:
case GFX7_DATAPORT_DC_UNTYPED_ATOMIC_OP:
return calculate_desc(info, unit_dp_dc, 2, 0, 0,
30 /* XXX */, 400 /* XXX */,
10 /* XXX */, 100 /* XXX */,
@ -1190,7 +1190,7 @@ namespace {
return dependency_id(dependency_id_grf0 + i);
} else if (r.file == MRF && devinfo->ver >= 7) {
const unsigned i = GEN7_MRF_HACK_START +
const unsigned i = GFX7_MRF_HACK_START +
r.nr + r.offset / REG_SIZE + delta;
assert(i < dependency_id_mrf0 - dependency_id_grf0);
return dependency_id(dependency_id_grf0 + i);

2
src/intel/compiler/brw_reg.h
View file

@ -67,7 +67,7 @@ struct gen_device_info;
* register allocators have to be careful of this to avoid corrupting the "MRF"s
* with actual GRF allocations.
*/
#define GEN7_MRF_HACK_START 112
#define GFX7_MRF_HACK_START 112
/** Number of message register file registers */
#define BRW_MAX_MRF(gen) (gen == 6 ? 24 : 16)

228
src/intel/compiler/brw_reg_type.c
View file

@ -33,26 +33,26 @@ enum hw_reg_type {
BRW_HW_REG_TYPE_UW = 2,
BRW_HW_REG_TYPE_W = 3,
BRW_HW_REG_TYPE_F = 7,
GEN8_HW_REG_TYPE_UQ = 8,
GEN8_HW_REG_TYPE_Q = 9,
GFX8_HW_REG_TYPE_UQ = 8,
GFX8_HW_REG_TYPE_Q = 9,
BRW_HW_REG_TYPE_UB = 4,
BRW_HW_REG_TYPE_B = 5,
GEN7_HW_REG_TYPE_DF = 6,
GEN8_HW_REG_TYPE_HF = 10,
GFX7_HW_REG_TYPE_DF = 6,
GFX8_HW_REG_TYPE_HF = 10,
GEN11_HW_REG_TYPE_UD = 0,
GEN11_HW_REG_TYPE_D = 1,
GEN11_HW_REG_TYPE_UW = 2,
GEN11_HW_REG_TYPE_W = 3,
GEN11_HW_REG_TYPE_UB = 4,
GEN11_HW_REG_TYPE_B = 5,
GEN11_HW_REG_TYPE_UQ = 6,
GEN11_HW_REG_TYPE_Q = 7,
GEN11_HW_REG_TYPE_HF = 8,
GEN11_HW_REG_TYPE_F = 9,
GEN11_HW_REG_TYPE_DF = 10,
GEN11_HW_REG_TYPE_NF = 11,
GFX11_HW_REG_TYPE_UD = 0,
GFX11_HW_REG_TYPE_D = 1,
GFX11_HW_REG_TYPE_UW = 2,
GFX11_HW_REG_TYPE_W = 3,
GFX11_HW_REG_TYPE_UB = 4,
GFX11_HW_REG_TYPE_B = 5,
GFX11_HW_REG_TYPE_UQ = 6,
GFX11_HW_REG_TYPE_Q = 7,
GFX11_HW_REG_TYPE_HF = 8,
GFX11_HW_REG_TYPE_F = 9,
GFX11_HW_REG_TYPE_DF = 10,
GFX11_HW_REG_TYPE_NF = 11,
};
enum hw_imm_type {
@ -61,32 +61,32 @@ enum hw_imm_type {
BRW_HW_IMM_TYPE_UW = 2,
BRW_HW_IMM_TYPE_W = 3,
BRW_HW_IMM_TYPE_F = 7,
GEN8_HW_IMM_TYPE_UQ = 8,
GEN8_HW_IMM_TYPE_Q = 9,
GFX8_HW_IMM_TYPE_UQ = 8,
GFX8_HW_IMM_TYPE_Q = 9,
BRW_HW_IMM_TYPE_UV = 4,
BRW_HW_IMM_TYPE_VF = 5,
BRW_HW_IMM_TYPE_V = 6,
GEN8_HW_IMM_TYPE_DF = 10,
GEN8_HW_IMM_TYPE_HF = 11,
GFX8_HW_IMM_TYPE_DF = 10,
GFX8_HW_IMM_TYPE_HF = 11,
GEN11_HW_IMM_TYPE_UD = 0,
GEN11_HW_IMM_TYPE_D = 1,
GEN11_HW_IMM_TYPE_UW = 2,
GEN11_HW_IMM_TYPE_W = 3,
GEN11_HW_IMM_TYPE_UV = 4,
GEN11_HW_IMM_TYPE_V = 5,
GEN11_HW_IMM_TYPE_UQ = 6,
GEN11_HW_IMM_TYPE_Q = 7,
GEN11_HW_IMM_TYPE_HF = 8,
GEN11_HW_IMM_TYPE_F = 9,
GEN11_HW_IMM_TYPE_DF = 10,
GEN11_HW_IMM_TYPE_VF = 11,
GFX11_HW_IMM_TYPE_UD = 0,
GFX11_HW_IMM_TYPE_D = 1,
GFX11_HW_IMM_TYPE_UW = 2,
GFX11_HW_IMM_TYPE_W = 3,
GFX11_HW_IMM_TYPE_UV = 4,
GFX11_HW_IMM_TYPE_V = 5,
GFX11_HW_IMM_TYPE_UQ = 6,
GFX11_HW_IMM_TYPE_Q = 7,
GFX11_HW_IMM_TYPE_HF = 8,
GFX11_HW_IMM_TYPE_F = 9,
GFX11_HW_IMM_TYPE_DF = 10,
GFX11_HW_IMM_TYPE_VF = 11,
};
#define GEN12_HW_REG_TYPE_UINT(n) (n)
#define GEN12_HW_REG_TYPE_SINT(n) (0x4 | (n))
#define GEN12_HW_REG_TYPE_FLOAT(n) (0x8 | (n))
#define GFX12_HW_REG_TYPE_UINT(n) (n)
#define GFX12_HW_REG_TYPE_SINT(n) (0x4 | (n))
#define GFX12_HW_REG_TYPE_FLOAT(n) (0x8 | (n))
static const struct hw_type {
enum hw_reg_type reg_type;
@ -121,7 +121,7 @@ static const struct hw_type {
}, gen7_hw_type[] = {
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID },
[BRW_REGISTER_TYPE_DF] = { GEN7_HW_REG_TYPE_DF, INVALID },
[BRW_REGISTER_TYPE_DF] = { GFX7_HW_REG_TYPE_DF, INVALID },
[BRW_REGISTER_TYPE_F] = { BRW_HW_REG_TYPE_F, BRW_HW_IMM_TYPE_F },
[BRW_REGISTER_TYPE_VF] = { INVALID, BRW_HW_IMM_TYPE_VF },
@ -136,13 +136,13 @@ static const struct hw_type {
}, gen8_hw_type[] = {
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID },
[BRW_REGISTER_TYPE_DF] = { GEN7_HW_REG_TYPE_DF, GEN8_HW_IMM_TYPE_DF },
[BRW_REGISTER_TYPE_DF] = { GFX7_HW_REG_TYPE_DF, GFX8_HW_IMM_TYPE_DF },
[BRW_REGISTER_TYPE_F] = { BRW_HW_REG_TYPE_F, BRW_HW_IMM_TYPE_F },
[BRW_REGISTER_TYPE_HF] = { GEN8_HW_REG_TYPE_HF, GEN8_HW_IMM_TYPE_HF },
[BRW_REGISTER_TYPE_HF] = { GFX8_HW_REG_TYPE_HF, GFX8_HW_IMM_TYPE_HF },
[BRW_REGISTER_TYPE_VF] = { INVALID, BRW_HW_IMM_TYPE_VF },
[BRW_REGISTER_TYPE_Q] = { GEN8_HW_REG_TYPE_Q, GEN8_HW_IMM_TYPE_Q },
[BRW_REGISTER_TYPE_UQ] = { GEN8_HW_REG_TYPE_UQ, GEN8_HW_IMM_TYPE_UQ },
[BRW_REGISTER_TYPE_Q] = { GFX8_HW_REG_TYPE_Q, GFX8_HW_IMM_TYPE_Q },
[BRW_REGISTER_TYPE_UQ] = { GFX8_HW_REG_TYPE_UQ, GFX8_HW_IMM_TYPE_UQ },
[BRW_REGISTER_TYPE_D] = { BRW_HW_REG_TYPE_D, BRW_HW_IMM_TYPE_D },
[BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD },
[BRW_REGISTER_TYPE_W] = { BRW_HW_REG_TYPE_W, BRW_HW_IMM_TYPE_W },
@ -154,34 +154,34 @@ static const struct hw_type {
}, gen11_hw_type[] = {
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID },
[BRW_REGISTER_TYPE_NF] = { GEN11_HW_REG_TYPE_NF, INVALID },
[BRW_REGISTER_TYPE_F] = { GEN11_HW_REG_TYPE_F, GEN11_HW_IMM_TYPE_F },
[BRW_REGISTER_TYPE_HF] = { GEN11_HW_REG_TYPE_HF, GEN11_HW_IMM_TYPE_HF },
[BRW_REGISTER_TYPE_VF] = { INVALID, GEN11_HW_IMM_TYPE_VF },
[BRW_REGISTER_TYPE_NF] = { GFX11_HW_REG_TYPE_NF, INVALID },
[BRW_REGISTER_TYPE_F] = { GFX11_HW_REG_TYPE_F, GFX11_HW_IMM_TYPE_F },
[BRW_REGISTER_TYPE_HF] = { GFX11_HW_REG_TYPE_HF, GFX11_HW_IMM_TYPE_HF },
[BRW_REGISTER_TYPE_VF] = { INVALID, GFX11_HW_IMM_TYPE_VF },
[BRW_REGISTER_TYPE_D] = { GEN11_HW_REG_TYPE_D, GEN11_HW_IMM_TYPE_D },
[BRW_REGISTER_TYPE_UD] = { GEN11_HW_REG_TYPE_UD, GEN11_HW_IMM_TYPE_UD },
[BRW_REGISTER_TYPE_W] = { GEN11_HW_REG_TYPE_W, GEN11_HW_IMM_TYPE_W },
[BRW_REGISTER_TYPE_UW] = { GEN11_HW_REG_TYPE_UW, GEN11_HW_IMM_TYPE_UW },
[BRW_REGISTER_TYPE_B] = { GEN11_HW_REG_TYPE_B, INVALID },
[BRW_REGISTER_TYPE_UB] = { GEN11_HW_REG_TYPE_UB, INVALID },
[BRW_REGISTER_TYPE_V] = { INVALID, GEN11_HW_IMM_TYPE_V },
[BRW_REGISTER_TYPE_UV] = { INVALID, GEN11_HW_IMM_TYPE_UV },
[BRW_REGISTER_TYPE_D] = { GFX11_HW_REG_TYPE_D, GFX11_HW_IMM_TYPE_D },
[BRW_REGISTER_TYPE_UD] = { GFX11_HW_REG_TYPE_UD, GFX11_HW_IMM_TYPE_UD },
[BRW_REGISTER_TYPE_W] = { GFX11_HW_REG_TYPE_W, GFX11_HW_IMM_TYPE_W },
[BRW_REGISTER_TYPE_UW] = { GFX11_HW_REG_TYPE_UW, GFX11_HW_IMM_TYPE_UW },
[BRW_REGISTER_TYPE_B] = { GFX11_HW_REG_TYPE_B, INVALID },
[BRW_REGISTER_TYPE_UB] = { GFX11_HW_REG_TYPE_UB, INVALID },
[BRW_REGISTER_TYPE_V] = { INVALID, GFX11_HW_IMM_TYPE_V },
[BRW_REGISTER_TYPE_UV] = { INVALID, GFX11_HW_IMM_TYPE_UV },
}, gen12_hw_type[] = {
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID },
[BRW_REGISTER_TYPE_F] = { GEN12_HW_REG_TYPE_FLOAT(2), GEN12_HW_REG_TYPE_FLOAT(2) },
[BRW_REGISTER_TYPE_HF] = { GEN12_HW_REG_TYPE_FLOAT(1), GEN12_HW_REG_TYPE_FLOAT(1) },
[BRW_REGISTER_TYPE_VF] = { INVALID, GEN12_HW_REG_TYPE_FLOAT(0) },
[BRW_REGISTER_TYPE_F] = { GFX12_HW_REG_TYPE_FLOAT(2), GFX12_HW_REG_TYPE_FLOAT(2) },
[BRW_REGISTER_TYPE_HF] = { GFX12_HW_REG_TYPE_FLOAT(1), GFX12_HW_REG_TYPE_FLOAT(1) },
[BRW_REGISTER_TYPE_VF] = { INVALID, GFX12_HW_REG_TYPE_FLOAT(0) },
[BRW_REGISTER_TYPE_D] = { GEN12_HW_REG_TYPE_SINT(2), GEN12_HW_REG_TYPE_SINT(2) },
[BRW_REGISTER_TYPE_UD] = { GEN12_HW_REG_TYPE_UINT(2), GEN12_HW_REG_TYPE_UINT(2) },
[BRW_REGISTER_TYPE_W] = { GEN12_HW_REG_TYPE_SINT(1), GEN12_HW_REG_TYPE_SINT(1) },
[BRW_REGISTER_TYPE_UW] = { GEN12_HW_REG_TYPE_UINT(1), GEN12_HW_REG_TYPE_UINT(1) },
[BRW_REGISTER_TYPE_B] = { GEN12_HW_REG_TYPE_SINT(0), INVALID },
[BRW_REGISTER_TYPE_UB] = { GEN12_HW_REG_TYPE_UINT(0), INVALID },
[BRW_REGISTER_TYPE_V] = { INVALID, GEN12_HW_REG_TYPE_SINT(0) },
[BRW_REGISTER_TYPE_UV] = { INVALID, GEN12_HW_REG_TYPE_UINT(0) },
[BRW_REGISTER_TYPE_D] = { GFX12_HW_REG_TYPE_SINT(2), GFX12_HW_REG_TYPE_SINT(2) },
[BRW_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), GFX12_HW_REG_TYPE_UINT(2) },
[BRW_REGISTER_TYPE_W] = { GFX12_HW_REG_TYPE_SINT(1), GFX12_HW_REG_TYPE_SINT(1) },
[BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), GFX12_HW_REG_TYPE_UINT(1) },
[BRW_REGISTER_TYPE_B] = { GFX12_HW_REG_TYPE_SINT(0), INVALID },
[BRW_REGISTER_TYPE_UB] = { GFX12_HW_REG_TYPE_UINT(0), INVALID },
[BRW_REGISTER_TYPE_V] = { INVALID, GFX12_HW_REG_TYPE_SINT(0) },
[BRW_REGISTER_TYPE_UV] = { INVALID, GFX12_HW_REG_TYPE_UINT(0) },
};
/* SNB adds 3-src instructions (MAD and LRP) that only operate on floats, so
@ -194,26 +194,26 @@ static const struct hw_type {
* for most register types.
*/
enum hw_3src_reg_type {
GEN7_3SRC_TYPE_F = 0,
GEN7_3SRC_TYPE_D = 1,
GEN7_3SRC_TYPE_UD = 2,
GEN7_3SRC_TYPE_DF = 3,
GEN8_3SRC_TYPE_HF = 4,
GFX7_3SRC_TYPE_F = 0,
GFX7_3SRC_TYPE_D = 1,
GFX7_3SRC_TYPE_UD = 2,
GFX7_3SRC_TYPE_DF = 3,
GFX8_3SRC_TYPE_HF = 4,
/** When ExecutionDatatype is 1: @{ */
GEN10_ALIGN1_3SRC_REG_TYPE_HF = 0b000,
GEN10_ALIGN1_3SRC_REG_TYPE_F = 0b001,
GEN10_ALIGN1_3SRC_REG_TYPE_DF = 0b010,
GEN11_ALIGN1_3SRC_REG_TYPE_NF = 0b011,
GFX10_ALIGN1_3SRC_REG_TYPE_HF = 0b000,
GFX10_ALIGN1_3SRC_REG_TYPE_F = 0b001,
GFX10_ALIGN1_3SRC_REG_TYPE_DF = 0b010,
GFX11_ALIGN1_3SRC_REG_TYPE_NF = 0b011,
/** @} */
/** When ExecutionDatatype is 0: @{ */
GEN10_ALIGN1_3SRC_REG_TYPE_UD = 0b000,
GEN10_ALIGN1_3SRC_REG_TYPE_D = 0b001,
GEN10_ALIGN1_3SRC_REG_TYPE_UW = 0b010,
GEN10_ALIGN1_3SRC_REG_TYPE_W = 0b011,
GEN10_ALIGN1_3SRC_REG_TYPE_UB = 0b100,
GEN10_ALIGN1_3SRC_REG_TYPE_B = 0b101,
GFX10_ALIGN1_3SRC_REG_TYPE_UD = 0b000,
GFX10_ALIGN1_3SRC_REG_TYPE_D = 0b001,
GFX10_ALIGN1_3SRC_REG_TYPE_UW = 0b010,
GFX10_ALIGN1_3SRC_REG_TYPE_W = 0b011,
GFX10_ALIGN1_3SRC_REG_TYPE_UB = 0b100,
GFX10_ALIGN1_3SRC_REG_TYPE_B = 0b101,
/** @} */
};
@ -223,61 +223,61 @@ static const struct hw_3src_type {
} gen6_hw_3src_type[] = {
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID },
[BRW_REGISTER_TYPE_F] = { GEN7_3SRC_TYPE_F },
[BRW_REGISTER_TYPE_F] = { GFX7_3SRC_TYPE_F },
}, gen7_hw_3src_type[] = {
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID },
[BRW_REGISTER_TYPE_F] = { GEN7_3SRC_TYPE_F },
[BRW_REGISTER_TYPE_D] = { GEN7_3SRC_TYPE_D },
[BRW_REGISTER_TYPE_UD] = { GEN7_3SRC_TYPE_UD },
[BRW_REGISTER_TYPE_DF] = { GEN7_3SRC_TYPE_DF },
[BRW_REGISTER_TYPE_F] = { GFX7_3SRC_TYPE_F },
[BRW_REGISTER_TYPE_D] = { GFX7_3SRC_TYPE_D },
[BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD },
[BRW_REGISTER_TYPE_DF] = { GFX7_3SRC_TYPE_DF },
}, gen8_hw_3src_type[] = {
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID },
[BRW_REGISTER_TYPE_F] = { GEN7_3SRC_TYPE_F },
[BRW_REGISTER_TYPE_D] = { GEN7_3SRC_TYPE_D },
[BRW_REGISTER_TYPE_UD] = { GEN7_3SRC_TYPE_UD },
[BRW_REGISTER_TYPE_DF] = { GEN7_3SRC_TYPE_DF },
[BRW_REGISTER_TYPE_HF] = { GEN8_3SRC_TYPE_HF },
[BRW_REGISTER_TYPE_F] = { GFX7_3SRC_TYPE_F },
[BRW_REGISTER_TYPE_D] = { GFX7_3SRC_TYPE_D },
[BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD },
[BRW_REGISTER_TYPE_DF] = { GFX7_3SRC_TYPE_DF },
[BRW_REGISTER_TYPE_HF] = { GFX8_3SRC_TYPE_HF },
}, gen10_hw_3src_align1_type[] = {
#define E(x) BRW_ALIGN1_3SRC_EXEC_TYPE_##x
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID },
[BRW_REGISTER_TYPE_DF] = { GEN10_ALIGN1_3SRC_REG_TYPE_DF, E(FLOAT) },
[BRW_REGISTER_TYPE_F] = { GEN10_ALIGN1_3SRC_REG_TYPE_F, E(FLOAT) },
[BRW_REGISTER_TYPE_HF] = { GEN10_ALIGN1_3SRC_REG_TYPE_HF, E(FLOAT) },
[BRW_REGISTER_TYPE_DF] = { GFX10_ALIGN1_3SRC_REG_TYPE_DF, E(FLOAT) },
[BRW_REGISTER_TYPE_F] = { GFX10_ALIGN1_3SRC_REG_TYPE_F, E(FLOAT) },
[BRW_REGISTER_TYPE_HF] = { GFX10_ALIGN1_3SRC_REG_TYPE_HF, E(FLOAT) },
[BRW_REGISTER_TYPE_D] = { GEN10_ALIGN1_3SRC_REG_TYPE_D, E(INT) },
[BRW_REGISTER_TYPE_UD] = { GEN10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) },
[BRW_REGISTER_TYPE_W] = { GEN10_ALIGN1_3SRC_REG_TYPE_W, E(INT) },
[BRW_REGISTER_TYPE_UW] = { GEN10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
[BRW_REGISTER_TYPE_B] = { GEN10_ALIGN1_3SRC_REG_TYPE_B, E(INT) },
[BRW_REGISTER_TYPE_UB] = { GEN10_ALIGN1_3SRC_REG_TYPE_UB, E(INT) },
[BRW_REGISTER_TYPE_D] = { GFX10_ALIGN1_3SRC_REG_TYPE_D, E(INT) },
[BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) },
[BRW_REGISTER_TYPE_W] = { GFX10_ALIGN1_3SRC_REG_TYPE_W, E(INT) },
[BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
[BRW_REGISTER_TYPE_B] = { GFX10_ALIGN1_3SRC_REG_TYPE_B, E(INT) },
[BRW_REGISTER_TYPE_UB] = { GFX10_ALIGN1_3SRC_REG_TYPE_UB, E(INT) },
}, gen11_hw_3src_type[] = {
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID },
[BRW_REGISTER_TYPE_NF] = { GEN11_ALIGN1_3SRC_REG_TYPE_NF, E(FLOAT) },
[BRW_REGISTER_TYPE_F] = { GEN10_ALIGN1_3SRC_REG_TYPE_F, E(FLOAT) },
[BRW_REGISTER_TYPE_HF] = { GEN10_ALIGN1_3SRC_REG_TYPE_HF, E(FLOAT) },
[BRW_REGISTER_TYPE_NF] = { GFX11_ALIGN1_3SRC_REG_TYPE_NF, E(FLOAT) },
[BRW_REGISTER_TYPE_F] = { GFX10_ALIGN1_3SRC_REG_TYPE_F, E(FLOAT) },
[BRW_REGISTER_TYPE_HF] = { GFX10_ALIGN1_3SRC_REG_TYPE_HF, E(FLOAT) },
[BRW_REGISTER_TYPE_D] = { GEN10_ALIGN1_3SRC_REG_TYPE_D, E(INT) },
[BRW_REGISTER_TYPE_UD] = { GEN10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) },
[BRW_REGISTER_TYPE_W] = { GEN10_ALIGN1_3SRC_REG_TYPE_W, E(INT) },
[BRW_REGISTER_TYPE_UW] = { GEN10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
[BRW_REGISTER_TYPE_B] = { GEN10_ALIGN1_3SRC_REG_TYPE_B, E(INT) },
[BRW_REGISTER_TYPE_UB] = { GEN10_ALIGN1_3SRC_REG_TYPE_UB, E(INT) },
[BRW_REGISTER_TYPE_D] = { GFX10_ALIGN1_3SRC_REG_TYPE_D, E(INT) },
[BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) },
[BRW_REGISTER_TYPE_W] = { GFX10_ALIGN1_3SRC_REG_TYPE_W, E(INT) },
[BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
[BRW_REGISTER_TYPE_B] = { GFX10_ALIGN1_3SRC_REG_TYPE_B, E(INT) },
[BRW_REGISTER_TYPE_UB] = { GFX10_ALIGN1_3SRC_REG_TYPE_UB, E(INT) },
}, gen12_hw_3src_type[] = {
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID },
[BRW_REGISTER_TYPE_F] = { GEN12_HW_REG_TYPE_UINT(2), E(FLOAT), },
[BRW_REGISTER_TYPE_HF] = { GEN12_HW_REG_TYPE_UINT(1), E(FLOAT), },
[BRW_REGISTER_TYPE_F] = { GFX12_HW_REG_TYPE_UINT(2), E(FLOAT), },
[BRW_REGISTER_TYPE_HF] = { GFX12_HW_REG_TYPE_UINT(1), E(FLOAT), },
[BRW_REGISTER_TYPE_D] = { GEN12_HW_REG_TYPE_SINT(2), E(INT), },
[BRW_REGISTER_TYPE_UD] = { GEN12_HW_REG_TYPE_UINT(2), E(INT), },
[BRW_REGISTER_TYPE_W] = { GEN12_HW_REG_TYPE_SINT(1), E(INT), },
[BRW_REGISTER_TYPE_UW] = { GEN12_HW_REG_TYPE_UINT(1), E(INT), },
[BRW_REGISTER_TYPE_B] = { GEN12_HW_REG_TYPE_SINT(0), E(INT), },
[BRW_REGISTER_TYPE_UB] = { GEN12_HW_REG_TYPE_UINT(0), E(INT), },
[BRW_REGISTER_TYPE_D] = { GFX12_HW_REG_TYPE_SINT(2), E(INT), },
[BRW_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), E(INT), },
[BRW_REGISTER_TYPE_W] = { GFX12_HW_REG_TYPE_SINT(1), E(INT), },
[BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
[BRW_REGISTER_TYPE_B] = { GFX12_HW_REG_TYPE_SINT(0), E(INT), },
[BRW_REGISTER_TYPE_UB] = { GFX12_HW_REG_TYPE_UINT(0), E(INT), },
#undef E
};

60
src/intel/compiler/brw_schedule_instructions.cpp
View file

@ -368,13 +368,13 @@ schedule_node::set_latency_gen7(bool is_haswell)
break;
case VEC4_OPCODE_UNTYPED_ATOMIC:
/* See GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP */
/* See GFX7_DATAPORT_DC_UNTYPED_ATOMIC_OP */
latency = 14000;
break;
case VEC4_OPCODE_UNTYPED_SURFACE_READ:
case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
/* See also GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ */
/* See also GFX7_DATAPORT_DC_UNTYPED_SURFACE_READ */
latency = is_haswell ? 300 : 600;
break;
@ -383,8 +383,8 @@ schedule_node::set_latency_gen7(bool is_haswell)
case BRW_SFID_SAMPLER: {
unsigned msg_type = (inst->desc >> 12) & 0x1f;
switch (msg_type) {
case GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO:
case GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO:
case GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO:
case GFX6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO:
/* See also SHADER_OPCODE_TXS */
latency = 100;
break;
@ -397,22 +397,22 @@ schedule_node::set_latency_gen7(bool is_haswell)
break;
}
case GEN6_SFID_DATAPORT_RENDER_CACHE:
case GFX6_SFID_DATAPORT_RENDER_CACHE:
switch ((inst->desc >> 14) & 0x1f) {
case GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE:
case GEN7_DATAPORT_RC_TYPED_SURFACE_READ:
case GFX7_DATAPORT_RC_TYPED_SURFACE_WRITE:
case GFX7_DATAPORT_RC_TYPED_SURFACE_READ:
/* See also SHADER_OPCODE_TYPED_SURFACE_READ */
assert(!is_haswell);
latency = 600;
break;
case GEN7_DATAPORT_RC_TYPED_ATOMIC_OP:
case GFX7_DATAPORT_RC_TYPED_ATOMIC_OP:
/* See also SHADER_OPCODE_TYPED_ATOMIC */
assert(!is_haswell);
latency = 14000;
break;
case GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE:
case GFX6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE:
/* completely fabricated number */
latency = 600;
break;
@ -422,19 +422,19 @@ schedule_node::set_latency_gen7(bool is_haswell)
}
break;
case GEN7_SFID_DATAPORT_DATA_CACHE:
case GFX7_SFID_DATAPORT_DATA_CACHE:
switch ((inst->desc >> 14) & 0x1f) {
case BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ:
case GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ:
case GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE:
case GFX7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ:
case GFX6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE:
/* We have no data for this but assume it's a little faster than
* untyped surface read/write.
*/
latency = 200;
break;
case GEN7_DATAPORT_DC_DWORD_SCATTERED_READ:
case GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE:
case GFX7_DATAPORT_DC_DWORD_SCATTERED_READ:
case GFX6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE:
case HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ:
case HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE:
/* We have no data for this but assume it's roughly the same as
@ -443,8 +443,8 @@ schedule_node::set_latency_gen7(bool is_haswell)
latency = 300;
break;
case GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ:
case GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE:
case GFX7_DATAPORT_DC_UNTYPED_SURFACE_READ:
case GFX7_DATAPORT_DC_UNTYPED_SURFACE_WRITE:
/* Test code:
* mov(8) g112<1>UD 0x00000000UD { align1 WE_all 1Q };
* mov(1) g112.7<1>UD g1.7<0,1,0>UD { align1 WE_all };
@ -468,7 +468,7 @@ schedule_node::set_latency_gen7(bool is_haswell)
latency = 600;
break;
case GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP:
case GFX7_DATAPORT_DC_UNTYPED_ATOMIC_OP:
/* Test code:
* mov(8) g112<1>ud 0x00000000ud { align1 WE_all 1Q };
* mov(1) g112.7<1>ud g1.7<0,1,0>ud { align1 WE_all };
@ -498,13 +498,13 @@ schedule_node::set_latency_gen7(bool is_haswell)
case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE:
case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ:
case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE:
case GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE:
case GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ:
case GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE:
case GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ:
case GEN9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_READ:
case GEN9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_WRITE:
/* See also GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ */
case GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE:
case GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ:
case GFX8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE:
case GFX9_DATAPORT_DC_PORT1_A64_SCATTERED_READ:
case GFX9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_READ:
case GFX9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_WRITE:
/* See also GFX7_DATAPORT_DC_UNTYPED_SURFACE_READ */
latency = 300;
break;
@ -512,12 +512,12 @@ schedule_node::set_latency_gen7(bool is_haswell)
case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2:
case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2:
case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP:
case GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP:
case GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP:
case GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP:
case GEN12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_INT_OP:
case GEN12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_FLOAT_OP:
/* See also GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP */
case GFX9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP:
case GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP:
case GFX9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP:
case GFX12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_INT_OP:
case GFX12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_FLOAT_OP:
/* See also GFX7_DATAPORT_DC_UNTYPED_ATOMIC_OP */
latency = 14000;
break;

2
src/intel/compiler/brw_shader.cpp
View file

@ -1333,7 +1333,7 @@ brw_compile_tes(const struct brw_compiler *compiler,
unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
assert(output_size_bytes >= 1);
if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
if (output_size_bytes > GFX7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
if (error_str)
*error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
return NULL;

56
src/intel/compiler/brw_vec4_generator.cpp
View file

@ -122,9 +122,9 @@ generate_tex(struct brw_codegen *p,
case SHADER_OPCODE_TEX:
case SHADER_OPCODE_TXL:
if (inst->shadow_compare) {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
} else {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LOD;
}
break;
case SHADER_OPCODE_TXD:
@ -133,41 +133,41 @@ generate_tex(struct brw_codegen *p,
assert(devinfo->is_haswell);
msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
} else {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
}
break;
case SHADER_OPCODE_TXF:
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LD;
break;
case SHADER_OPCODE_TXF_CMS:
if (devinfo->ver >= 7)
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
else
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LD;
break;
case SHADER_OPCODE_TXF_MCS:
assert(devinfo->ver >= 7);
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
break;
case SHADER_OPCODE_TXS:
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
break;
case SHADER_OPCODE_TG4:
if (inst->shadow_compare) {
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
} else {
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
}
break;
case SHADER_OPCODE_TG4_OFFSET:
if (inst->shadow_compare) {
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
} else {
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
}
break;
case SHADER_OPCODE_SAMPLEINFO:
msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
msg_type = GFX6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
break;
default:
unreachable("should not get here: invalid vec4 texture opcode");
@ -637,17 +637,17 @@ static void
generate_gs_get_instance_id(struct brw_codegen *p,
struct brw_reg dst)
{
/* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
/* We want to right shift R0.0 & R0.1 by GFX7_GS_PAYLOAD_INSTANCE_ID_SHIFT
* and store into dst.0 & dst.4. So generate the instruction:
*
* shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
* shr(8) dst<1> R0<1,4,0> GFX7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
*/
brw_push_insn_state(p);
brw_set_default_access_mode(p, BRW_ALIGN_1);
dst = retype(dst, BRW_REGISTER_TYPE_UD);
struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
brw_SHR(p, dst, stride(r0, 1, 4, 0),
brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT));
brw_imm_ud(GFX7_GS_PAYLOAD_INSTANCE_ID_SHIFT));
brw_pop_insn_state(p);
}
@ -1157,15 +1157,15 @@ generate_scratch_read(struct brw_codegen *p,
uint32_t msg_type;
if (devinfo->ver >= 6)
msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
msg_type = GFX6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
else if (devinfo->ver == 5 || devinfo->is_g4x)
msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
else
msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
const unsigned target_cache =
devinfo->ver >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
devinfo->ver >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
devinfo->ver >= 7 ? GFX7_SFID_DATAPORT_DATA_CACHE :
devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE :
BRW_SFID_DATAPORT_READ;
/* Each of the 8 channel enables is considered for whether each
@ -1194,8 +1194,8 @@ generate_scratch_write(struct brw_codegen *p,
{
const struct gen_device_info *devinfo = p->devinfo;
const unsigned target_cache =
(devinfo->ver >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
devinfo->ver >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
(devinfo->ver >= 7 ? GFX7_SFID_DATAPORT_DATA_CACHE :
devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE :
BRW_SFID_DATAPORT_WRITE);
struct brw_reg header = brw_vec8_grf(0, 0);
bool write_commit;
@ -1217,9 +1217,9 @@ generate_scratch_write(struct brw_codegen *p,
uint32_t msg_type;
if (devinfo->ver >= 7)
msg_type = GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE;
msg_type = GFX7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE;
else if (devinfo->ver == 6)
msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
msg_type = GFX6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
else
msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
@ -1272,7 +1272,7 @@ generate_pull_constant_load(struct brw_codegen *p,
{
const struct gen_device_info *devinfo = p->devinfo;
const unsigned target_cache =
(devinfo->ver >= 6 ? GEN6_SFID_DATAPORT_SAMPLER_CACHE :
(devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_SAMPLER_CACHE :
BRW_SFID_DATAPORT_READ);
assert(index.file == BRW_IMMEDIATE_VALUE &&
index.type == BRW_REGISTER_TYPE_UD);
@ -1301,7 +1301,7 @@ generate_pull_constant_load(struct brw_codegen *p,
uint32_t msg_type;
if (devinfo->ver >= 6)
msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
msg_type = GFX6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
else if (devinfo->ver == 5 || devinfo->is_g4x)
msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
else
@ -1341,7 +1341,7 @@ generate_get_buffer_size(struct brw_codegen *p,
src,
surf_index.ud,
0,
GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
1, /* response length */
inst->mlen,
inst->header_size > 0,
@ -1369,7 +1369,7 @@ generate_pull_constant_load_gen7(struct brw_codegen *p,
brw_message_desc(devinfo, inst->mlen, 1, inst->header_size) |
brw_sampler_desc(devinfo, surf_index.ud,
0, /* LD message ignores sampler unit */
GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
GFX5_SAMPLER_MESSAGE_SAMPLE_LD,
BRW_SAMPLER_SIMD_MODE_SIMD4X2, 0));
} else {
@ -1395,7 +1395,7 @@ generate_pull_constant_load_gen7(struct brw_codegen *p,
brw_sampler_desc(devinfo,
0 /* surface */,
0 /* sampler */,
GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
GFX5_SAMPLER_MESSAGE_SAMPLE_LD,
BRW_SAMPLER_SIMD_MODE_SIMD4X2,
0),
false /* EOT */);

14
src/intel/compiler/brw_vec4_gs_visitor.cpp
View file

@ -501,7 +501,7 @@ vec4_gs_visitor::gs_emit_vertex(int stream_id)
*/
if (c->control_data_header_size_bits > 0 &&
gs_prog_data->control_data_format ==
GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID) {
GFX7_GS_CONTROL_DATA_FORMAT_GSCTL_SID) {
this->current_annotation = "emit vertex: Stream control data bits";
set_stream_control_data_bits(stream_id);
}
@ -517,7 +517,7 @@ vec4_gs_visitor::gs_end_primitive()
* output type is points, in which case EndPrimitive() is a no-op.
*/
if (gs_prog_data->control_data_format !=
GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT) {
GFX7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT) {
return;
}
@ -641,7 +641,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
* to multiple streams, and EndPrimitive() has no effect. So we
* configure the hardware to interpret the control data as stream ID.
*/
prog_data->control_data_format = GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID;
prog_data->control_data_format = GFX7_GS_CONTROL_DATA_FORMAT_GSCTL_SID;
/* We only have to emit control bits if we are using non-zero streams */
if (nir->info.gs.active_stream_mask != (1 << 0))
@ -655,7 +655,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
* streams is not supported. So we configure the hardware to interpret
* the control data as EndPrimitive information (a.k.a. "cut bits").
*/
prog_data->control_data_format = GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT;
prog_data->control_data_format = GFX7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT;
/* We only need to output control data if the shader actually calls
* EndPrimitive().
@ -724,7 +724,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
*/
unsigned output_vertex_size_bytes = prog_data->base.vue_map.num_slots * 16;
assert(compiler->devinfo->ver == 6 ||
output_vertex_size_bytes <= GEN7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES);
output_vertex_size_bytes <= GFX7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES);
prog_data->output_vertex_size_hwords =
ALIGN(output_vertex_size_bytes, 32) / 32;
@ -782,9 +782,9 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
if (output_size_bytes == 0)
output_size_bytes = 1;
unsigned max_output_size_bytes = GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES;
unsigned max_output_size_bytes = GFX7_MAX_GS_URB_ENTRY_SIZE_BYTES;
if (compiler->devinfo->ver == 6)
max_output_size_bytes = GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES;
max_output_size_bytes = GFX6_MAX_GS_URB_ENTRY_SIZE_BYTES;
if (output_size_bytes > max_output_size_bytes)
return NULL;

2
src/intel/compiler/brw_vec4_nir.cpp
View file

@ -706,7 +706,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
const dst_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD);
vec4_instruction *fence =
bld.emit(SHADER_OPCODE_MEMORY_FENCE, tmp, brw_vec8_grf(0, 0));
fence->sfid = GEN7_SFID_DATAPORT_DATA_CACHE;
fence->sfid = GFX7_SFID_DATAPORT_DATA_CACHE;
break;
}

2
src/intel/compiler/brw_vec4_reg_allocate.cpp
View file

@ -92,7 +92,7 @@ extern "C" void
brw_vec4_alloc_reg_set(struct brw_compiler *compiler)
{
int base_reg_count =
compiler->devinfo->ver >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
compiler->devinfo->ver >= 7 ? GFX7_MRF_HACK_START : BRW_MAX_GRF;
/* After running split_virtual_grfs(), almost all VGRFs will be of size 1.
* SEND-from-GRF sources cannot be split, so we also need classes for each

2
src/intel/compiler/brw_vec4_tcs.cpp
View file

@ -438,7 +438,7 @@ brw_compile_tcs(const struct brw_compiler *compiler,
num_per_vertex_slots * 16;
assert(output_size_bytes >= 1);
if (output_size_bytes > GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES)
if (output_size_bytes > GFX7_MAX_HS_URB_ENTRY_SIZE_BYTES)
return NULL;
/* URB entry sizes are stored as a multiple of 64 bytes. */

2
src/intel/compiler/brw_vec4_visitor.cpp
View file

@ -1785,7 +1785,7 @@ vec4_visitor::vec4_visitor(const struct brw_compiler *compiler,
memset(this->output_num_components, 0, sizeof(this->output_num_components));
this->max_grf = devinfo->ver >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
this->max_grf = devinfo->ver >= 7 ? GFX7_MRF_HACK_START : BRW_MAX_GRF;
this->uniforms = 0;

4
src/intel/compiler/gfx6_gs_visitor.cpp
View file

@ -125,7 +125,7 @@ gen6_gs_visitor::emit_prolog()
*
* So, what we do is to place PrimitiveID information in r1, which is always
* delivered as part of the payload, but its only populated with data
* relevant for transform feedback when we set GEN6_GS_SVBI_PAYLOAD_ENABLE
* relevant for transform feedback when we set GFX6_GS_SVBI_PAYLOAD_ENABLE
* in the 3DSTATE_GS state packet. That information can be obtained by other
* means though, so we can safely use r1 for this purpose.
*/
@ -505,7 +505,7 @@ gen6_gs_visitor::setup_payload()
reg++;
/* r1 is always part of the payload and it holds information relevant
* for transform feedback when we set the GEN6_GS_SVBI_PAYLOAD_ENABLE bit in
* for transform feedback when we set the GFX6_GS_SVBI_PAYLOAD_ENABLE bit in
* the 3DSTATE_GS packet. We will overwrite it with the PrimitiveID
* information (and move the original value to a virtual register if
* necessary).

4
src/intel/compiler/test_eu_compact.cpp
View file

@ -277,9 +277,9 @@ struct {
{ gen_ADD_GRF_GRF_GRF, GEN_ALL },
{ gen_ADD_GRF_GRF_IMM, GEN_ALL },
{ gen_ADD_GRF_GRF_IMM_d, GEN_ALL },
{ gen_ADD_MRF_GRF_GRF, GEN_LE(GEN6) },
{ gen_ADD_MRF_GRF_GRF, GEN_LE(GFX6) },
{ gen_ADD_vec1_GRF_GRF_GRF, GEN_ALL },
{ gen_PLN_MRF_GRF_GRF, GEN_LE(GEN6) },
{ gen_PLN_MRF_GRF_GRF, GEN_LE(GFX6) },
{ gen_f0_0_MOV_GRF_GRF, GEN_ALL },
{ gen_f0_1_MOV_GRF_GRF, GEN_ALL },
};

170
src/intel/dev/gen_device_info.c
View file

@ -209,7 +209,7 @@ static const struct gen_device_info gen_device_info_snb_gt2 = {
.cs_prefetch_size = 512,
};
#define GEN7_FEATURES \
#define GFX7_FEATURES \
.ver = 7, \
.has_hiz_and_separate_stencil = true, \
.must_use_separate_stencil = true, \
@ -221,7 +221,7 @@ static const struct gen_device_info gen_device_info_snb_gt2 = {
.cs_prefetch_size = 512
static const struct gen_device_info gen_device_info_ivb_gt1 = {
GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
GFX7_FEATURES, .is_ivybridge = true, .gt = 1,
.num_slices = 1,
.num_subslices = { 1, },
.num_eu_per_subslice = 6,
@ -249,7 +249,7 @@ static const struct gen_device_info gen_device_info_ivb_gt1 = {
};
static const struct gen_device_info gen_device_info_ivb_gt2 = {
GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
GFX7_FEATURES, .is_ivybridge = true, .gt = 2,
.num_slices = 1,
.num_subslices = { 1, },
.num_eu_per_subslice = 12,
@ -278,7 +278,7 @@ static const struct gen_device_info gen_device_info_ivb_gt2 = {
};
static const struct gen_device_info gen_device_info_byt = {
GEN7_FEATURES, .is_baytrail = true, .gt = 1,
GFX7_FEATURES, .is_baytrail = true, .gt = 1,
.num_slices = 1,
.num_subslices = { 1, },
.num_eu_per_subslice = 4,
@ -307,7 +307,7 @@ static const struct gen_device_info gen_device_info_byt = {
};
#define HSW_FEATURES \
GEN7_FEATURES, \
GFX7_FEATURES, \
.is_haswell = true, \
.verx10 = 75, \
.supports_simd16_3src = true, \
@ -397,10 +397,10 @@ static const struct gen_device_info gen_device_info_hsw_gt3 = {
.simulator_id = 9,
};
/* It's unclear how well supported sampling from the hiz buffer is on GEN8,
/* It's unclear how well supported sampling from the hiz buffer is on GFX8,
* so keep things conservative for now and set has_sample_with_hiz = false.
*/
#define GEN8_FEATURES \
#define GFX8_FEATURES \
.ver = 8, \
.has_hiz_and_separate_stencil = true, \
.has_resource_streamer = true, \
@ -423,7 +423,7 @@ static const struct gen_device_info gen_device_info_hsw_gt3 = {
.cs_prefetch_size = 512
static const struct gen_device_info gen_device_info_bdw_gt1 = {
GEN8_FEATURES, .gt = 1,
GFX8_FEATURES, .gt = 1,
.is_broadwell = true,
.num_slices = 1,
.num_subslices = { 2, },
@ -447,7 +447,7 @@ static const struct gen_device_info gen_device_info_bdw_gt1 = {
};
static const struct gen_device_info gen_device_info_bdw_gt2 = {
GEN8_FEATURES, .gt = 2,
GFX8_FEATURES, .gt = 2,
.is_broadwell = true,
.num_slices = 1,
.num_subslices = { 3, },
@ -470,7 +470,7 @@ static const struct gen_device_info gen_device_info_bdw_gt2 = {
};
static const struct gen_device_info gen_device_info_bdw_gt3 = {
GEN8_FEATURES, .gt = 3,
GFX8_FEATURES, .gt = 3,
.is_broadwell = true,
.num_slices = 2,
.num_subslices = { 3, 3, },
@ -493,7 +493,7 @@ static const struct gen_device_info gen_device_info_bdw_gt3 = {
};
static const struct gen_device_info gen_device_info_chv = {
GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
GFX8_FEATURES, .is_cherryview = 1, .gt = 1,
.has_llc = false,
.has_integer_dword_mul = false,
.num_slices = 1,
@ -521,7 +521,7 @@ static const struct gen_device_info gen_device_info_chv = {
.simulator_id = 13,
};
#define GEN9_HW_INFO \
#define GFX9_HW_INFO \
.ver = 9, \
.max_vs_threads = 336, \
.max_gs_threads = 336, \
@ -543,9 +543,9 @@ static const struct gen_device_info gen_device_info_chv = {
}, \
}
#define GEN9_LP_FEATURES \
GEN8_FEATURES, \
GEN9_HW_INFO, \
#define GFX9_LP_FEATURES \
GFX8_FEATURES, \
GFX9_HW_INFO, \
.has_integer_dword_mul = false, \
.gt = 1, \
.has_llc = false, \
@ -571,13 +571,13 @@ static const struct gen_device_info gen_device_info_chv = {
}, \
}
#define GEN9_LP_FEATURES_3X6 \
GEN9_LP_FEATURES, \
#define GFX9_LP_FEATURES_3X6 \
GFX9_LP_FEATURES, \
.num_subslices = { 3, }, \
.num_eu_per_subslice = 6
#define GEN9_LP_FEATURES_2X6 \
GEN9_LP_FEATURES, \
#define GFX9_LP_FEATURES_2X6 \
GFX9_LP_FEATURES, \
.num_subslices = { 2, }, \
.num_eu_per_subslice = 6, \
.max_vs_threads = 56, \
@ -598,13 +598,13 @@ static const struct gen_device_info gen_device_info_chv = {
}, \
}
#define GEN9_FEATURES \
GEN8_FEATURES, \
GEN9_HW_INFO, \
#define GFX9_FEATURES \
GFX8_FEATURES, \
GFX9_HW_INFO, \
.has_sample_with_hiz = true
static const struct gen_device_info gen_device_info_skl_gt1 = {
GEN9_FEATURES, .gt = 1,
GFX9_FEATURES, .gt = 1,
.is_skylake = true,
.num_slices = 1,
.num_subslices = { 2, },
@ -618,7 +618,7 @@ static const struct gen_device_info gen_device_info_skl_gt1 = {
};
static const struct gen_device_info gen_device_info_skl_gt2 = {
GEN9_FEATURES, .gt = 2,
GFX9_FEATURES, .gt = 2,
.is_skylake = true,
.num_slices = 1,
.num_subslices = { 3, },
@ -628,7 +628,7 @@ static const struct gen_device_info gen_device_info_skl_gt2 = {
};
static const struct gen_device_info gen_device_info_skl_gt3 = {
GEN9_FEATURES, .gt = 3,
GFX9_FEATURES, .gt = 3,
.is_skylake = true,
.num_slices = 2,
.num_subslices = { 3, 3, },
@ -638,7 +638,7 @@ static const struct gen_device_info gen_device_info_skl_gt3 = {
};
static const struct gen_device_info gen_device_info_skl_gt4 = {
GEN9_FEATURES, .gt = 4,
GFX9_FEATURES, .gt = 4,
.is_skylake = true,
.num_slices = 3,
.num_subslices = { 3, 3, 3, },
@ -656,25 +656,25 @@ static const struct gen_device_info gen_device_info_skl_gt4 = {
};
static const struct gen_device_info gen_device_info_bxt = {
GEN9_LP_FEATURES_3X6,
GFX9_LP_FEATURES_3X6,
.is_broxton = true,
.l3_banks = 2,
.simulator_id = 14,
};
static const struct gen_device_info gen_device_info_bxt_2x6 = {
GEN9_LP_FEATURES_2X6,
GFX9_LP_FEATURES_2X6,
.is_broxton = true,
.l3_banks = 1,
.simulator_id = 14,
};
/*
* Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
* There's no KBL entry. Using the default SKL (GEN9) GS entries value.
* There's no KBL entry. Using the default SKL (GFX9) GS entries value.
*/
static const struct gen_device_info gen_device_info_kbl_gt1 = {
GEN9_FEATURES,
GFX9_FEATURES,
.is_kabylake = true,
.gt = 1,
@ -692,7 +692,7 @@ static const struct gen_device_info gen_device_info_kbl_gt1 = {
};
static const struct gen_device_info gen_device_info_kbl_gt1_5 = {
GEN9_FEATURES,
GFX9_FEATURES,
.is_kabylake = true,
.gt = 1,
@ -705,7 +705,7 @@ static const struct gen_device_info gen_device_info_kbl_gt1_5 = {
};
static const struct gen_device_info gen_device_info_kbl_gt2 = {
GEN9_FEATURES,
GFX9_FEATURES,
.is_kabylake = true,
.gt = 2,
@ -717,7 +717,7 @@ static const struct gen_device_info gen_device_info_kbl_gt2 = {
};
static const struct gen_device_info gen_device_info_kbl_gt3 = {
GEN9_FEATURES,
GFX9_FEATURES,
.is_kabylake = true,
.gt = 3,
@ -729,7 +729,7 @@ static const struct gen_device_info gen_device_info_kbl_gt3 = {
};
static const struct gen_device_info gen_device_info_kbl_gt4 = {
GEN9_FEATURES,
GFX9_FEATURES,
.is_kabylake = true,
.gt = 4,
@ -751,21 +751,21 @@ static const struct gen_device_info gen_device_info_kbl_gt4 = {
};
static const struct gen_device_info gen_device_info_glk = {
GEN9_LP_FEATURES_3X6,
GFX9_LP_FEATURES_3X6,
.is_geminilake = true,
.l3_banks = 2,
.simulator_id = 17,
};
static const struct gen_device_info gen_device_info_glk_2x6 = {
GEN9_LP_FEATURES_2X6,
GFX9_LP_FEATURES_2X6,
.is_geminilake = true,
.l3_banks = 2,
.simulator_id = 17,
};
static const struct gen_device_info gen_device_info_cfl_gt1 = {
GEN9_FEATURES,
GFX9_FEATURES,
.is_coffeelake = true,
.gt = 1,
@ -781,7 +781,7 @@ static const struct gen_device_info gen_device_info_cfl_gt1 = {
.simulator_id = 24,
};
static const struct gen_device_info gen_device_info_cfl_gt2 = {
GEN9_FEATURES,
GFX9_FEATURES,
.is_coffeelake = true,
.gt = 2,
@ -793,7 +793,7 @@ static const struct gen_device_info gen_device_info_cfl_gt2 = {
};
static const struct gen_device_info gen_device_info_cfl_gt3 = {
GEN9_FEATURES,
GFX9_FEATURES,
.is_coffeelake = true,
.gt = 3,
@ -806,7 +806,7 @@ static const struct gen_device_info gen_device_info_cfl_gt3 = {
#define subslices(args...) { args, }
#define GEN11_HW_INFO \
#define GFX11_HW_INFO \
.ver = 11, \
.has_pln = false, \
.max_vs_threads = 364, \
@ -816,9 +816,9 @@ static const struct gen_device_info gen_device_info_cfl_gt3 = {
.max_cs_threads = 56, \
.cs_prefetch_size = 512
#define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
GEN8_FEATURES, \
GEN11_HW_INFO, \
#define GFX11_FEATURES(_gt, _slices, _subslices, _l3) \
GFX8_FEATURES, \
GFX11_HW_INFO, \
.has_64bit_float = false, \
.has_64bit_int = false, \
.has_integer_dword_mul = false, \
@ -827,7 +827,7 @@ static const struct gen_device_info gen_device_info_cfl_gt3 = {
.num_subslices = _subslices, \
.num_eu_per_subslice = 8
#define GEN11_URB_MIN_MAX_ENTRIES \
#define GFX11_URB_MIN_MAX_ENTRIES \
.min_entries = { \
[MESA_SHADER_VERTEX] = 64, \
[MESA_SHADER_TESS_EVAL] = 34, \
@ -840,80 +840,80 @@ static const struct gen_device_info gen_device_info_cfl_gt3 = {
}
static const struct gen_device_info gen_device_info_icl_gt2 = {
GEN11_FEATURES(2, 1, subslices(8), 8),
GFX11_FEATURES(2, 1, subslices(8), 8),
.urb = {
GEN11_URB_MIN_MAX_ENTRIES,
GFX11_URB_MIN_MAX_ENTRIES,
},
.simulator_id = 19,
};
static const struct gen_device_info gen_device_info_icl_gt1_5 = {
GEN11_FEATURES(1, 1, subslices(6), 6),
GFX11_FEATURES(1, 1, subslices(6), 6),
.urb = {
GEN11_URB_MIN_MAX_ENTRIES,
GFX11_URB_MIN_MAX_ENTRIES,
},
.simulator_id = 19,
};
static const struct gen_device_info gen_device_info_icl_gt1 = {
GEN11_FEATURES(1, 1, subslices(4), 6),
GFX11_FEATURES(1, 1, subslices(4), 6),
.urb = {
GEN11_URB_MIN_MAX_ENTRIES,
GFX11_URB_MIN_MAX_ENTRIES,
},
.simulator_id = 19,
};
static const struct gen_device_info gen_device_info_icl_gt0_5 = {
GEN11_FEATURES(1, 1, subslices(1), 6),
GFX11_FEATURES(1, 1, subslices(1), 6),
.urb = {
GEN11_URB_MIN_MAX_ENTRIES,
GFX11_URB_MIN_MAX_ENTRIES,
},
.simulator_id = 19,
};
#define GEN11_LP_FEATURES \
#define GFX11_LP_FEATURES \
.is_elkhartlake = true, \
.urb = { \
GEN11_URB_MIN_MAX_ENTRIES, \
GFX11_URB_MIN_MAX_ENTRIES, \
}, \
.disable_ccs_repack = true, \
.simulator_id = 28
static const struct gen_device_info gen_device_info_ehl_4x8 = {
GEN11_FEATURES(1, 1, subslices(4), 4),
GEN11_LP_FEATURES,
GFX11_FEATURES(1, 1, subslices(4), 4),
GFX11_LP_FEATURES,
};
static const struct gen_device_info gen_device_info_ehl_4x6 = {
GEN11_FEATURES(1, 1, subslices(4), 4),
GEN11_LP_FEATURES,
GFX11_FEATURES(1, 1, subslices(4), 4),
GFX11_LP_FEATURES,
.num_eu_per_subslice = 6,
};
static const struct gen_device_info gen_device_info_ehl_4x5 = {
GEN11_FEATURES(1, 1, subslices(4), 4),
GEN11_LP_FEATURES,
GFX11_FEATURES(1, 1, subslices(4), 4),
GFX11_LP_FEATURES,
.num_eu_per_subslice = 5,
};
static const struct gen_device_info gen_device_info_ehl_4x4 = {
GEN11_FEATURES(1, 1, subslices(4), 4),
GEN11_LP_FEATURES,
GFX11_FEATURES(1, 1, subslices(4), 4),
GFX11_LP_FEATURES,
.num_eu_per_subslice = 4,
};
static const struct gen_device_info gen_device_info_ehl_2x8 = {
GEN11_FEATURES(1, 1, subslices(2), 4),
GEN11_LP_FEATURES,
GFX11_FEATURES(1, 1, subslices(2), 4),
GFX11_LP_FEATURES,
};
static const struct gen_device_info gen_device_info_ehl_2x4 = {
GEN11_FEATURES(1, 1, subslices(2), 4),
GEN11_LP_FEATURES,
GFX11_FEATURES(1, 1, subslices(2), 4),
GFX11_LP_FEATURES,
.num_eu_per_subslice =4,
};
#define GEN12_URB_MIN_MAX_ENTRIES \
#define GFX12_URB_MIN_MAX_ENTRIES \
.min_entries = { \
[MESA_SHADER_VERTEX] = 64, \
[MESA_SHADER_TESS_EVAL] = 34, \
@ -925,7 +925,7 @@ static const struct gen_device_info gen_device_info_ehl_2x4 = {
[MESA_SHADER_GEOMETRY] = 1548, \
}
#define GEN12_HW_INFO \
#define GFX12_HW_INFO \
.ver = 12, \
.has_pln = false, \
.has_sample_with_hiz = false, \
@ -936,12 +936,12 @@ static const struct gen_device_info gen_device_info_ehl_2x4 = {
.max_tes_threads = 546, \
.max_cs_threads = 112, /* threads per DSS */ \
.urb = { \
GEN12_URB_MIN_MAX_ENTRIES, \
GFX12_URB_MIN_MAX_ENTRIES, \
}
#define GEN12_FEATURES(_gt, _slices, _l3) \
GEN8_FEATURES, \
GEN12_HW_INFO, \
#define GFX12_FEATURES(_gt, _slices, _l3) \
GFX8_FEATURES, \
GFX12_HW_INFO, \
.has_64bit_float = false, \
.has_64bit_int = false, \
.has_integer_dword_mul = false, \
@ -952,53 +952,53 @@ static const struct gen_device_info gen_device_info_ehl_2x4 = {
#define dual_subslices(args...) { args, }
#define GEN12_GT05_FEATURES \
GEN12_FEATURES(1, 1, 4), \
#define GFX12_GT05_FEATURES \
GFX12_FEATURES(1, 1, 4), \
.num_subslices = dual_subslices(1)
#define GEN12_GT_FEATURES(_gt) \
GEN12_FEATURES(_gt, 1, _gt == 1 ? 4 : 8), \
#define GFX12_GT_FEATURES(_gt) \
GFX12_FEATURES(_gt, 1, _gt == 1 ? 4 : 8), \
.num_subslices = dual_subslices(_gt == 1 ? 2 : 6)
static const struct gen_device_info gen_device_info_tgl_gt1 = {
GEN12_GT_FEATURES(1),
GFX12_GT_FEATURES(1),
.is_tigerlake = true,
};
static const struct gen_device_info gen_device_info_tgl_gt2 = {
GEN12_GT_FEATURES(2),
GFX12_GT_FEATURES(2),
.is_tigerlake = true,
};
static const struct gen_device_info gen_device_info_rkl_gt05 = {
GEN12_GT05_FEATURES,
GFX12_GT05_FEATURES,
.is_rocketlake = true,
};
static const struct gen_device_info gen_device_info_rkl_gt1 = {
GEN12_GT_FEATURES(1),
GFX12_GT_FEATURES(1),
.is_rocketlake = true,
};
static const struct gen_device_info gen_device_info_adl_gt05 = {
GEN12_GT05_FEATURES,
GFX12_GT05_FEATURES,
.is_alderlake = true,
};
static const struct gen_device_info gen_device_info_adl_gt1 = {
GEN12_GT_FEATURES(1),
GFX12_GT_FEATURES(1),
.is_alderlake = true,
};
#define GEN12_DG1_FEATURES \
GEN12_GT_FEATURES(2), \
#define GFX12_DG1_FEATURES \
GFX12_GT_FEATURES(2), \
.is_dg1 = true, \
.has_llc = false, \
.urb.size = 768, \
.simulator_id = 30
UNUSED static const struct gen_device_info gen_device_info_dg1 = {
GEN12_DG1_FEATURES,
GFX12_DG1_FEATURES,
};
static void

2
src/intel/genxml/gen_bits_header.py
View file

@ -148,7 +148,7 @@ class Gen(object):
if token[0] == '_':
token = token[1:]
return 'GEN{}_{}'.format(gen, token)
return 'GFX{}_{}'.format(gen, token)
class Container(object):

22
src/intel/genxml/gen_macros.h
View file

@ -60,37 +60,37 @@
/* Prefixing macros */
#if (GFX_VERx10 == 40)
# define GENX(X) GEN4_##X
# define GENX(X) GFX4_##X
# define genX(x) gen4_##x
#elif (GFX_VERx10 == 45)
# define GENX(X) GEN45_##X
# define GENX(X) GFX45_##X
# define genX(x) gen45_##x
#elif (GFX_VERx10 == 50)
# define GENX(X) GEN5_##X
# define GENX(X) GFX5_##X
# define genX(x) gen5_##x
#elif (GFX_VERx10 == 60)
# define GENX(X) GEN6_##X
# define GENX(X) GFX6_##X
# define genX(x) gen6_##x
#elif (GFX_VERx10 == 70)
# define GENX(X) GEN7_##X
# define GENX(X) GFX7_##X
# define genX(x) gen7_##x
#elif (GFX_VERx10 == 75)
# define GENX(X) GEN75_##X
# define GENX(X) GFX75_##X
# define genX(x) gen75_##x
#elif (GFX_VERx10 == 80)
# define GENX(X) GEN8_##X
# define GENX(X) GFX8_##X
# define genX(x) gen8_##x
#elif (GFX_VERx10 == 90)
# define GENX(X) GEN9_##X
# define GENX(X) GFX9_##X
# define genX(x) gen9_##x
#elif (GFX_VERx10 == 110)
# define GENX(X) GEN11_##X
# define GENX(X) GFX11_##X
# define genX(x) gen11_##x
#elif (GFX_VERx10 == 120)
# define GENX(X) GEN12_##X
# define GENX(X) GFX12_##X
# define genX(x) gen12_##x
#elif (GFX_VERx10 == 125)
# define GENX(X) GEN125_##X
# define GENX(X) GFX125_##X
# define genX(x) gen125_##x
#else
# error "Need to add prefixing macros for this gen"

4
src/intel/genxml/gen_pack_header.py
View file

@ -516,8 +516,8 @@ class Parser(object):
def gen_prefix(self, name):
if name[0] == "_":
return 'GEN%s%s' % (self.gen, name)
return 'GEN%s_%s' % (self.gen, name)
return 'GFX%s%s' % (self.gen, name)
return 'GFX%s_%s' % (self.gen, name)
def gen_guard(self):
return self.gen_prefix("PACK_H")

4
src/intel/isl/isl.c
View file

@ -267,7 +267,7 @@ isl_device_init(struct isl_device *dev,
}
if (ISL_GFX_VER(dev) >= 12) {
dev->ds.size += GEN12_MI_LOAD_REGISTER_IMM_length * 4 * 2;
dev->ds.size += GFX12_MI_LOAD_REGISTER_IMM_length * 4 * 2;
}
isl_device_setup_mocs(dev);
@ -1246,7 +1246,7 @@ isl_calc_phys_total_extent_el_gen4_3d(
total_h += level_h * max_layers_vert;
}
/* GEN4_3D layouts don't really have an array pitch since each LOD has a
/* GFX4_3D layouts don't really have an array pitch since each LOD has a
* different number of horizontal and vertical layers. We have to set it
* to something, so at least make it true for LOD0.
*/

48
src/intel/perf/gen_perf.c
View file

@ -519,35 +519,35 @@ load_pipeline_statistic_metrics(struct gen_perf_config *perf_cfg,
"N vertex shader invocations");
if (devinfo->ver == 6) {
gen_perf_query_add_stat_reg(query, GEN6_SO_PRIM_STORAGE_NEEDED, 1, 1,
gen_perf_query_add_stat_reg(query, GFX6_SO_PRIM_STORAGE_NEEDED, 1, 1,
"SO_PRIM_STORAGE_NEEDED",
"N geometry shader stream-out primitives (total)");
gen_perf_query_add_stat_reg(query, GEN6_SO_NUM_PRIMS_WRITTEN, 1, 1,
gen_perf_query_add_stat_reg(query, GFX6_SO_NUM_PRIMS_WRITTEN, 1, 1,
"SO_NUM_PRIMS_WRITTEN",
"N geometry shader stream-out primitives (written)");
} else {
gen_perf_query_add_stat_reg(query, GEN7_SO_PRIM_STORAGE_NEEDED(0), 1, 1,
gen_perf_query_add_stat_reg(query, GFX7_SO_PRIM_STORAGE_NEEDED(0), 1, 1,
"SO_PRIM_STORAGE_NEEDED (Stream 0)",
"N stream-out (stream 0) primitives (total)");
gen_perf_query_add_stat_reg(query, GEN7_SO_PRIM_STORAGE_NEEDED(1), 1, 1,
gen_perf_query_add_stat_reg(query, GFX7_SO_PRIM_STORAGE_NEEDED(1), 1, 1,
"SO_PRIM_STORAGE_NEEDED (Stream 1)",
"N stream-out (stream 1) primitives (total)");
gen_perf_query_add_stat_reg(query, GEN7_SO_PRIM_STORAGE_NEEDED(2), 1, 1,
gen_perf_query_add_stat_reg(query, GFX7_SO_PRIM_STORAGE_NEEDED(2), 1, 1,
"SO_PRIM_STORAGE_NEEDED (Stream 2)",
"N stream-out (stream 2) primitives (total)");
gen_perf_query_add_stat_reg(query, GEN7_SO_PRIM_STORAGE_NEEDED(3), 1, 1,
gen_perf_query_add_stat_reg(query, GFX7_SO_PRIM_STORAGE_NEEDED(3), 1, 1,
"SO_PRIM_STORAGE_NEEDED (Stream 3)",
"N stream-out (stream 3) primitives (total)");
gen_perf_query_add_stat_reg(query, GEN7_SO_NUM_PRIMS_WRITTEN(0), 1, 1,
gen_perf_query_add_stat_reg(query, GFX7_SO_NUM_PRIMS_WRITTEN(0), 1, 1,
"SO_NUM_PRIMS_WRITTEN (Stream 0)",
"N stream-out (stream 0) primitives (written)");
gen_perf_query_add_stat_reg(query, GEN7_SO_NUM_PRIMS_WRITTEN(1), 1, 1,
gen_perf_query_add_stat_reg(query, GFX7_SO_NUM_PRIMS_WRITTEN(1), 1, 1,
"SO_NUM_PRIMS_WRITTEN (Stream 1)",
"N stream-out (stream 1) primitives (written)");
gen_perf_query_add_stat_reg(query, GEN7_SO_NUM_PRIMS_WRITTEN(2), 1, 1,
gen_perf_query_add_stat_reg(query, GFX7_SO_NUM_PRIMS_WRITTEN(2), 1, 1,
"SO_NUM_PRIMS_WRITTEN (Stream 2)",
"N stream-out (stream 2) primitives (written)");
gen_perf_query_add_stat_reg(query, GEN7_SO_NUM_PRIMS_WRITTEN(3), 1, 1,
gen_perf_query_add_stat_reg(query, GFX7_SO_NUM_PRIMS_WRITTEN(3), 1, 1,
"SO_NUM_PRIMS_WRITTEN (Stream 3)",
"N stream-out (stream 3) primitives (written)");
}
@ -1119,14 +1119,14 @@ gen_perf_query_result_read_gt_frequency(struct gen_perf_query_result *result,
switch (devinfo->ver) {
case 7:
case 8:
result->gt_frequency[0] = GET_FIELD(start, GEN7_RPSTAT1_CURR_GT_FREQ) * 50ULL;
result->gt_frequency[1] = GET_FIELD(end, GEN7_RPSTAT1_CURR_GT_FREQ) * 50ULL;
result->gt_frequency[0] = GET_FIELD(start, GFX7_RPSTAT1_CURR_GT_FREQ) * 50ULL;
result->gt_frequency[1] = GET_FIELD(end, GFX7_RPSTAT1_CURR_GT_FREQ) * 50ULL;
break;
case 9:
case 11:
case 12:
result->gt_frequency[0] = GET_FIELD(start, GEN9_RPSTAT0_CURR_GT_FREQ) * 50ULL / 3ULL;
result->gt_frequency[1] = GET_FIELD(end, GEN9_RPSTAT0_CURR_GT_FREQ) * 50ULL / 3ULL;
result->gt_frequency[0] = GET_FIELD(start, GFX9_RPSTAT0_CURR_GT_FREQ) * 50ULL / 3ULL;
result->gt_frequency[1] = GET_FIELD(end, GFX9_RPSTAT0_CURR_GT_FREQ) * 50ULL / 3ULL;
break;
default:
unreachable("unexpected gen");
@ -1329,33 +1329,33 @@ gen_perf_init_query_fields(struct gen_perf_config *perf_cfg,
if (devinfo->ver == 8 && !devinfo->is_cherryview) {
add_query_register(layout,
GEN_PERF_QUERY_FIELD_TYPE_SRM_RPSTAT,
GEN7_RPSTAT1, 4, 0);
GFX7_RPSTAT1, 4, 0);
}
if (devinfo->ver >= 9) {
add_query_register(layout,
GEN_PERF_QUERY_FIELD_TYPE_SRM_RPSTAT,
GEN9_RPSTAT0, 4, 0);
GFX9_RPSTAT0, 4, 0);
}
if (!can_use_mi_rpc_bc_counters(devinfo)) {
if (devinfo->ver >= 8 && devinfo->ver <= 11) {
for (uint32_t i = 0; i < GEN8_N_OA_PERF_B32; i++) {
for (uint32_t i = 0; i < GFX8_N_OA_PERF_B32; i++) {
add_query_register(layout, GEN_PERF_QUERY_FIELD_TYPE_SRM_OA_B,
GEN8_OA_PERF_B32(i), 4, i);
GFX8_OA_PERF_B32(i), 4, i);
}
for (uint32_t i = 0; i < GEN8_N_OA_PERF_C32; i++) {
for (uint32_t i = 0; i < GFX8_N_OA_PERF_C32; i++) {
add_query_register(layout, GEN_PERF_QUERY_FIELD_TYPE_SRM_OA_C,
GEN8_OA_PERF_C32(i), 4, i);
GFX8_OA_PERF_C32(i), 4, i);
}
} else if (devinfo->ver == 12) {
for (uint32_t i = 0; i < GEN12_N_OAG_PERF_B32; i++) {
for (uint32_t i = 0; i < GFX12_N_OAG_PERF_B32; i++) {
add_query_register(layout, GEN_PERF_QUERY_FIELD_TYPE_SRM_OA_B,
GEN12_OAG_PERF_B32(i), 4, i);
GFX12_OAG_PERF_B32(i), 4, i);
}
for (uint32_t i = 0; i < GEN12_N_OAG_PERF_C32; i++) {
for (uint32_t i = 0; i < GFX12_N_OAG_PERF_C32; i++) {
add_query_register(layout, GEN_PERF_QUERY_FIELD_TYPE_SRM_OA_C,
GEN12_OAG_PERF_C32(i), 4, i);
GFX12_OAG_PERF_C32(i), 4, i);
}
}
}

4
src/intel/perf/gen_perf_query.c
View file

@ -763,8 +763,8 @@ gen_perf_begin_query(struct gen_perf_context *perf_ctx,
/* The period_exponent gives a sampling period as follows:
* sample_period = timestamp_period * 2^(period_exponent + 1)
*
* The timestamps increments every 80ns (HSW), ~52ns (GEN9LP) or
* ~83ns (GEN8/9).
* The timestamps increments every 80ns (HSW), ~52ns (GFX9LP) or
* ~83ns (GFX8/9).
*
* The counter overflow period is derived from the EuActive counter
* which reads a counter that increments by the number of clock

72
src/intel/perf/gen_perf_regs.h
View file

@ -27,17 +27,17 @@
#define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low))
/* GT core frequency counters */
#define GEN7_RPSTAT1 0xA01C
#define GEN7_RPSTAT1_CURR_GT_FREQ_SHIFT 7
#define GEN7_RPSTAT1_CURR_GT_FREQ_MASK INTEL_MASK(13, 7)
#define GEN7_RPSTAT1_PREV_GT_FREQ_SHIFT 0
#define GEN7_RPSTAT1_PREV_GT_FREQ_MASK INTEL_MASK(6, 0)
#define GFX7_RPSTAT1 0xA01C
#define GFX7_RPSTAT1_CURR_GT_FREQ_SHIFT 7
#define GFX7_RPSTAT1_CURR_GT_FREQ_MASK INTEL_MASK(13, 7)
#define GFX7_RPSTAT1_PREV_GT_FREQ_SHIFT 0
#define GFX7_RPSTAT1_PREV_GT_FREQ_MASK INTEL_MASK(6, 0)
#define GEN9_RPSTAT0 0xA01C
#define GEN9_RPSTAT0_CURR_GT_FREQ_SHIFT 23
#define GEN9_RPSTAT0_CURR_GT_FREQ_MASK INTEL_MASK(31, 23)
#define GEN9_RPSTAT0_PREV_GT_FREQ_SHIFT 0
#define GEN9_RPSTAT0_PREV_GT_FREQ_MASK INTEL_MASK(8, 0)
#define GFX9_RPSTAT0 0xA01C
#define GFX9_RPSTAT0_CURR_GT_FREQ_SHIFT 23
#define GFX9_RPSTAT0_CURR_GT_FREQ_MASK INTEL_MASK(31, 23)
#define GFX9_RPSTAT0_PREV_GT_FREQ_SHIFT 0
#define GFX9_RPSTAT0_PREV_GT_FREQ_MASK INTEL_MASK(8, 0)
/* Programmable perf 64bits counters (used for GTRequestQueueFull counter on
* gen7-11)
@ -47,30 +47,30 @@
#define PERF_CNT_VALUE_MASK ((1ull << 44) - 1)
/* Global OA perf counters */
#define GEN7_N_OA_PERF_A32 44
#define GEN7_OA_PERF_A32(idx) (0x2800 + (idx) * 4)
#define GFX7_N_OA_PERF_A32 44
#define GFX7_OA_PERF_A32(idx) (0x2800 + (idx) * 4)
#define GEN8_OA_PERF_TICKS 0x2910
#define GEN8_N_OA_PERF_A64 32
#define GEN8_N_OA_PERF_A32 4
#define GEN8_N_OA_PERF_B32 8
#define GEN8_N_OA_PERF_C32 8
#define GEN8_OA_PERF_A64_LDW(idx) (0x2800 + (idx) * 8)
#define GEN8_OA_PERF_A64_UDW(idx) (0x2800 + (idx) * 8 + 4)
#define GEN8_OA_PERF_A32(idx) (0x2900 + (idx) * 4)
#define GEN8_OA_PERF_B32(idx) (0x2920 + (idx) * 4)
#define GEN8_OA_PERF_C32(idx) (0x2940 + (idx) * 4)
#define GFX8_OA_PERF_TICKS 0x2910
#define GFX8_N_OA_PERF_A64 32
#define GFX8_N_OA_PERF_A32 4
#define GFX8_N_OA_PERF_B32 8
#define GFX8_N_OA_PERF_C32 8
#define GFX8_OA_PERF_A64_LDW(idx) (0x2800 + (idx) * 8)
#define GFX8_OA_PERF_A64_UDW(idx) (0x2800 + (idx) * 8 + 4)
#define GFX8_OA_PERF_A32(idx) (0x2900 + (idx) * 4)
#define GFX8_OA_PERF_B32(idx) (0x2920 + (idx) * 4)
#define GFX8_OA_PERF_C32(idx) (0x2940 + (idx) * 4)
#define GEN12_OAG_PERF_TICKS 0xda90
#define GEN12_N_OAG_PERF_A64 32
#define GEN12_N_OAG_PERF_A32 4
#define GEN12_N_OAG_PERF_B32 8
#define GEN12_N_OAG_PERF_C32 8
#define GEN12_OAG_PERF_A64_LDW(idx) (0xd980 + (idx) * 8)
#define GEN12_OAG_PERF_A64_UDW(idx) (0xd980 + (idx) * 8 + 4)
#define GEN12_OAG_PERF_A32(idx) (0xda80 + (idx) * 4)
#define GEN12_OAG_PERF_B32(idx) (0xda94 + (idx) * 4)
#define GEN12_OAG_PERF_C32(idx) (0xdab4 + (idx) * 4)
#define GFX12_OAG_PERF_TICKS 0xda90
#define GFX12_N_OAG_PERF_A64 32
#define GFX12_N_OAG_PERF_A32 4
#define GFX12_N_OAG_PERF_B32 8
#define GFX12_N_OAG_PERF_C32 8
#define GFX12_OAG_PERF_A64_LDW(idx) (0xd980 + (idx) * 8)
#define GFX12_OAG_PERF_A64_UDW(idx) (0xd980 + (idx) * 8 + 4)
#define GFX12_OAG_PERF_A32(idx) (0xda80 + (idx) * 4)
#define GFX12_OAG_PERF_B32(idx) (0xda94 + (idx) * 4)
#define GFX12_OAG_PERF_C32(idx) (0xdab4 + (idx) * 4)
/* Pipeline statistic counters */
#define IA_VERTICES_COUNT 0x2310
@ -87,9 +87,9 @@
#define PS_DEPTH_COUNT 0x2350
/* Stream-out counters */
#define GEN6_SO_PRIM_STORAGE_NEEDED 0x2280
#define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8)
#define GEN6_SO_NUM_PRIMS_WRITTEN 0x2288
#define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
#define GFX6_SO_PRIM_STORAGE_NEEDED 0x2280
#define GFX7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8)
#define GFX6_SO_NUM_PRIMS_WRITTEN 0x2288
#define GFX7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
#endif /* GEN_PERF_REGS_H */

8
src/intel/tools/aub_write.c
View file

@ -170,7 +170,7 @@ aub_file_init(struct aub_file *aub, FILE *file, FILE *debug, uint16_t pci_id, co
aub->pml4.phys_addr = aub->phys_addrs_allocator++ << 12;
mem_trace_memory_write_header_out(aub, aub->ggtt_addrs_allocator++,
GEN8_PTE_SIZE,
GFX8_PTE_SIZE,
AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_GGTT_ENTRY,
"GGTT PT");
dword_out(aub, 1);
@ -190,7 +190,7 @@ aub_file_finish(struct aub_file *aub)
uint32_t
aub_gtt_size(struct aub_file *aub)
{
return NUM_PT_ENTRIES * (aub->addr_bits > 32 ? GEN8_PTE_SIZE : PTE_SIZE);
return NUM_PT_ENTRIES * (aub->addr_bits > 32 ? GFX8_PTE_SIZE : PTE_SIZE);
}
static void
@ -405,8 +405,8 @@ aub_map_ggtt(struct aub_file *aub, uint64_t virt_addr, uint64_t size)
}
mem_trace_memory_write_header_out(aub,
(virt_addr >> 12) * GEN8_PTE_SIZE,
ggtt_ptes * GEN8_PTE_SIZE,
(virt_addr >> 12) * GFX8_PTE_SIZE,
ggtt_ptes * GFX8_PTE_SIZE,
AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_GGTT_ENTRY,
"GGTT PT");
for (uint32_t i = 0; i < ggtt_ptes; i++) {

18
src/intel/tools/gen_context.h
View file

@ -29,14 +29,14 @@
#define RING_SIZE (1 * 4096)
#define PPHWSP_SIZE (1 * 4096)
#define GEN11_LR_CONTEXT_RENDER_SIZE (14 * 4096)
#define GEN10_LR_CONTEXT_RENDER_SIZE (19 * 4096)
#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * 4096)
#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * 4096)
#define GEN8_LR_CONTEXT_OTHER_SIZE (2 * 4096)
#define GFX11_LR_CONTEXT_RENDER_SIZE (14 * 4096)
#define GFX10_LR_CONTEXT_RENDER_SIZE (19 * 4096)
#define GFX9_LR_CONTEXT_RENDER_SIZE (22 * 4096)
#define GFX8_LR_CONTEXT_RENDER_SIZE (20 * 4096)
#define GFX8_LR_CONTEXT_OTHER_SIZE (2 * 4096)
#define CONTEXT_RENDER_SIZE GEN9_LR_CONTEXT_RENDER_SIZE /* largest size */
#define CONTEXT_OTHER_SIZE GEN8_LR_CONTEXT_OTHER_SIZE
#define CONTEXT_RENDER_SIZE GFX9_LR_CONTEXT_RENDER_SIZE /* largest size */
#define CONTEXT_OTHER_SIZE GFX8_LR_CONTEXT_OTHER_SIZE
#define MI_LOAD_REGISTER_IMM_n(n) ((0x22 << 23) | (2 * (n) - 1))
#define MI_LRI_FORCE_POSTED (1<<12)
@ -70,10 +70,10 @@
#define MEMORY_MAP_SIZE (64 /* MiB */ * 1024 * 1024)
#define PTE_SIZE 4
#define GEN8_PTE_SIZE 8
#define GFX8_PTE_SIZE 8
#define NUM_PT_ENTRIES (ALIGN(MEMORY_MAP_SIZE, 4096) / 4096)
#define PT_SIZE ALIGN(NUM_PT_ENTRIES * GEN8_PTE_SIZE, 4096)
#define PT_SIZE ALIGN(NUM_PT_ENTRIES * GFX8_PTE_SIZE, 4096)
#define CONTEXT_FLAGS (0x339) /* Normal Priority | L3-LLC Coherency |
* PPGTT Enabled |

10
src/intel/tools/i965_gram.y
View file

@ -1066,14 +1066,14 @@ sharedfunction:
| URB { $$ = BRW_SFID_URB; }
| THREAD_SPAWNER { $$ = BRW_SFID_THREAD_SPAWNER; }
| VME { $$ = BRW_SFID_VME; }
| RENDER { $$ = GEN6_SFID_DATAPORT_RENDER_CACHE; }
| CONST { $$ = GEN6_SFID_DATAPORT_CONSTANT_CACHE; }
| DATA { $$ = GEN7_SFID_DATAPORT_DATA_CACHE; }
| PIXEL_INTERP { $$ = GEN7_SFID_PIXEL_INTERPOLATOR; }
| RENDER { $$ = GFX6_SFID_DATAPORT_RENDER_CACHE; }
| CONST { $$ = GFX6_SFID_DATAPORT_CONSTANT_CACHE; }
| DATA { $$ = GFX7_SFID_DATAPORT_DATA_CACHE; }
| PIXEL_INTERP { $$ = GFX7_SFID_PIXEL_INTERPOLATOR; }
| DP_DATA_1 { $$ = HSW_SFID_DATAPORT_DATA_CACHE_1; }
| CRE { $$ = HSW_SFID_CRE; }
| SAMPLER { $$ = BRW_SFID_SAMPLER; }
| DP_SAMPLER { $$ = GEN6_SFID_DATAPORT_SAMPLER_CACHE; }
| DP_SAMPLER { $$ = GFX6_SFID_DATAPORT_SAMPLER_CACHE; }
;
exp2:

4
src/intel/tools/i965_lex.l
View file

@ -136,7 +136,7 @@ cos { yylval.integer = BRW_MATH_FUNCTION_COS; return COS; }
exp { yylval.integer = BRW_MATH_FUNCTION_EXP; return EXP; }
fdiv { yylval.integer = BRW_MATH_FUNCTION_FDIV; return FDIV; }
inv { yylval.integer = BRW_MATH_FUNCTION_INV; return INV; }
invm { yylval.integer = GEN8_MATH_FUNCTION_INVM; return INVM; }
invm { yylval.integer = GFX8_MATH_FUNCTION_INVM; return INVM; }
intdiv {
yylval.integer = BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
return INTDIV;
@ -153,7 +153,7 @@ intmod {
log { yylval.integer = BRW_MATH_FUNCTION_LOG; return LOG; }
pow { yylval.integer = BRW_MATH_FUNCTION_POW; return POW; }
rsq { yylval.integer = BRW_MATH_FUNCTION_RSQ; return RSQ; }
rsqrtm { yylval.integer = GEN8_MATH_FUNCTION_RSQRTM; return RSQRTM; }
rsqrtm { yylval.integer = GFX8_MATH_FUNCTION_RSQRTM; return RSQRTM; }
sin { yylval.integer = BRW_MATH_FUNCTION_SIN; return SIN; }
sqrt { yylval.integer = BRW_MATH_FUNCTION_SQRT; return SQRT; }
sincos { yylval.integer = BRW_MATH_FUNCTION_SINCOS; return SINCOS; }

60
src/intel/vulkan/anv_batch_chain.c
View file

@ -476,7 +476,7 @@ anv_batch_bo_link(struct anv_cmd_buffer *cmd_buffer,
uint32_t next_bbo_offset)
{
const uint32_t bb_start_offset =
prev_bbo->length - GEN8_MI_BATCH_BUFFER_START_length * 4;
prev_bbo->length - GFX8_MI_BATCH_BUFFER_START_length * 4;
ASSERTED const uint32_t *bb_start = prev_bbo->bo->map + bb_start_offset;
/* Make sure we're looking at a MI_BATCH_BUFFER_START */
@ -577,15 +577,15 @@ emit_batch_buffer_start(struct anv_cmd_buffer *cmd_buffer,
* gens.
*/
#define GEN7_MI_BATCH_BUFFER_START_length 2
#define GEN7_MI_BATCH_BUFFER_START_length_bias 2
#define GFX7_MI_BATCH_BUFFER_START_length 2
#define GFX7_MI_BATCH_BUFFER_START_length_bias 2
const uint32_t gen7_length =
GEN7_MI_BATCH_BUFFER_START_length - GEN7_MI_BATCH_BUFFER_START_length_bias;
GFX7_MI_BATCH_BUFFER_START_length - GFX7_MI_BATCH_BUFFER_START_length_bias;
const uint32_t gen8_length =
GEN8_MI_BATCH_BUFFER_START_length - GEN8_MI_BATCH_BUFFER_START_length_bias;
GFX8_MI_BATCH_BUFFER_START_length - GFX8_MI_BATCH_BUFFER_START_length_bias;
anv_batch_emit(&cmd_buffer->batch, GEN8_MI_BATCH_BUFFER_START, bbs) {
anv_batch_emit(&cmd_buffer->batch, GFX8_MI_BATCH_BUFFER_START, bbs) {
bbs.DWordLength = cmd_buffer->device->info.ver < 8 ?
gen7_length : gen8_length;
bbs.SecondLevelBatchBuffer = Firstlevelbatch;
@ -606,7 +606,7 @@ cmd_buffer_chain_to_batch_bo(struct anv_cmd_buffer *cmd_buffer,
* have room for the chaining command. Since we're about to emit the
* chaining command, let's set it back where it should go.
*/
batch->end += GEN8_MI_BATCH_BUFFER_START_length * 4;
batch->end += GFX8_MI_BATCH_BUFFER_START_length * 4;
assert(batch->end == current_bbo->bo->map + current_bbo->bo->size);
emit_batch_buffer_start(cmd_buffer, bbo->bo, 0);
@ -627,8 +627,8 @@ anv_cmd_buffer_record_chain_submit(struct anv_cmd_buffer *cmd_buffer_from,
struct anv_batch_bo *first_bbo =
list_first_entry(&cmd_buffer_to->batch_bos, struct anv_batch_bo, link);
struct GEN8_MI_BATCH_BUFFER_START gen_bb_start = {
__anv_cmd_header(GEN8_MI_BATCH_BUFFER_START),
struct GFX8_MI_BATCH_BUFFER_START gen_bb_start = {
__anv_cmd_header(GFX8_MI_BATCH_BUFFER_START),
.SecondLevelBatchBuffer = Firstlevelbatch,
.AddressSpaceIndicator = ASI_PPGTT,
.BatchBufferStartAddress = (struct anv_address) { first_bbo->bo, 0 },
@ -640,7 +640,7 @@ anv_cmd_buffer_record_chain_submit(struct anv_cmd_buffer *cmd_buffer_from,
.alloc = &cmd_buffer_from->pool->alloc,
};
__anv_cmd_pack(GEN8_MI_BATCH_BUFFER_START)(&local_batch, bb_start, &gen_bb_start);
__anv_cmd_pack(GFX8_MI_BATCH_BUFFER_START)(&local_batch, bb_start, &gen_bb_start);
last_bbo->chained = true;
}
@ -655,8 +655,8 @@ anv_cmd_buffer_record_end_submit(struct anv_cmd_buffer *cmd_buffer)
last_bbo->chained = false;
uint32_t *batch = cmd_buffer->batch_end;
anv_pack_struct(batch, GEN8_MI_BATCH_BUFFER_END,
__anv_cmd_header(GEN8_MI_BATCH_BUFFER_END));
anv_pack_struct(batch, GFX8_MI_BATCH_BUFFER_END,
__anv_cmd_header(GFX8_MI_BATCH_BUFFER_END));
}
static VkResult
@ -680,7 +680,7 @@ anv_cmd_buffer_chain_batch(struct anv_batch *batch, void *_data)
list_addtail(&new_bbo->link, &cmd_buffer->batch_bos);
anv_batch_bo_start(new_bbo, batch, GEN8_MI_BATCH_BUFFER_START_length * 4);
anv_batch_bo_start(new_bbo, batch, GFX8_MI_BATCH_BUFFER_START_length * 4);
return VK_SUCCESS;
}
@ -692,7 +692,7 @@ anv_cmd_buffer_grow_batch(struct anv_batch *batch, void *_data)
struct anv_batch_bo *bbo = anv_cmd_buffer_current_batch_bo(cmd_buffer);
anv_batch_bo_grow(cmd_buffer, bbo, &cmd_buffer->batch, 4096,
GEN8_MI_BATCH_BUFFER_START_length * 4);
GFX8_MI_BATCH_BUFFER_START_length * 4);
return VK_SUCCESS;
}
@ -851,7 +851,7 @@ anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer)
}
anv_batch_bo_start(batch_bo, &cmd_buffer->batch,
GEN8_MI_BATCH_BUFFER_START_length * 4);
GFX8_MI_BATCH_BUFFER_START_length * 4);
int success = u_vector_init(&cmd_buffer->seen_bbos,
sizeof(struct anv_bo *),
@ -924,7 +924,7 @@ anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer)
anv_batch_bo_start(anv_cmd_buffer_current_batch_bo(cmd_buffer),
&cmd_buffer->batch,
GEN8_MI_BATCH_BUFFER_START_length * 4);
GFX8_MI_BATCH_BUFFER_START_length * 4);
while (u_vector_length(&cmd_buffer->bt_block_states) > 1) {
struct anv_state *bt_block = u_vector_remove(&cmd_buffer->bt_block_states);
@ -957,7 +957,7 @@ anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer)
* that padding before we end the batch; otherwise, we may end up
* with our BATCH_BUFFER_END in another BO.
*/
cmd_buffer->batch.end += GEN8_MI_BATCH_BUFFER_START_length * 4;
cmd_buffer->batch.end += GFX8_MI_BATCH_BUFFER_START_length * 4;
assert(cmd_buffer->batch.start == batch_bo->bo->map);
assert(cmd_buffer->batch.end == batch_bo->bo->map + batch_bo->bo->size);
@ -971,11 +971,11 @@ anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer)
if (batch_bo->chained)
emit_batch_buffer_start(cmd_buffer, batch_bo->bo, 0);
else
anv_batch_emit(&cmd_buffer->batch, GEN8_MI_BATCH_BUFFER_END, bbe);
anv_batch_emit(&cmd_buffer->batch, GFX8_MI_BATCH_BUFFER_END, bbe);
/* Round batch up to an even number of dwords. */
if ((cmd_buffer->batch.next - cmd_buffer->batch.start) & 4)
anv_batch_emit(&cmd_buffer->batch, GEN8_MI_NOOP, noop);
anv_batch_emit(&cmd_buffer->batch, GFX8_MI_NOOP, noop);
cmd_buffer->exec_mode = ANV_CMD_BUFFER_EXEC_MODE_PRIMARY;
} else {
@ -1003,16 +1003,16 @@ anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer)
cmd_buffer->batch.next - cmd_buffer->batch.start;
for (int32_t i = 0; i < (prefetch_len - batch_len); i += 4)
anv_batch_emit(&cmd_buffer->batch, GEN8_MI_NOOP, noop);
anv_batch_emit(&cmd_buffer->batch, GFX8_MI_NOOP, noop);
}
void *jump_addr =
anv_batch_emitn(&cmd_buffer->batch,
GEN8_MI_BATCH_BUFFER_START_length,
GEN8_MI_BATCH_BUFFER_START,
GFX8_MI_BATCH_BUFFER_START_length,
GFX8_MI_BATCH_BUFFER_START,
.AddressSpaceIndicator = ASI_PPGTT,
.SecondLevelBatchBuffer = Firstlevelbatch) +
(GEN8_MI_BATCH_BUFFER_START_BatchBufferStartAddress_start / 8);
(GFX8_MI_BATCH_BUFFER_START_BatchBufferStartAddress_start / 8);
cmd_buffer->return_addr = anv_batch_address(&cmd_buffer->batch, jump_addr);
/* The emit above may have caused us to chain batch buffers which
@ -1040,7 +1040,7 @@ anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer)
* have room for the chaining command. Since we're about to emit the
* chaining command, let's set it back where it should go.
*/
cmd_buffer->batch.end += GEN8_MI_BATCH_BUFFER_START_length * 4;
cmd_buffer->batch.end += GFX8_MI_BATCH_BUFFER_START_length * 4;
assert(cmd_buffer->batch.start == batch_bo->bo->map);
assert(cmd_buffer->batch.end == batch_bo->bo->map + batch_bo->bo->size);
@ -1082,7 +1082,7 @@ anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
struct anv_batch_bo *bbo = anv_cmd_buffer_current_batch_bo(primary);
unsigned length = secondary->batch.end - secondary->batch.start;
anv_batch_bo_grow(primary, bbo, &primary->batch, length,
GEN8_MI_BATCH_BUFFER_START_length * 4);
GFX8_MI_BATCH_BUFFER_START_length * 4);
anv_batch_emit_batch(&primary->batch, &secondary->batch);
break;
}
@ -1126,7 +1126,7 @@ anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
list_splicetail(&copy_list, &primary->batch_bos);
anv_batch_bo_continue(last_bbo, &primary->batch,
GEN8_MI_BATCH_BUFFER_START_length * 4);
GFX8_MI_BATCH_BUFFER_START_length * 4);
break;
}
case ANV_CMD_BUFFER_EXEC_MODE_CALL_AND_RETURN: {
@ -1135,10 +1135,10 @@ anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
uint64_t *write_return_addr =
anv_batch_emitn(&primary->batch,
GEN8_MI_STORE_DATA_IMM_length + 1 /* QWord write */,
GEN8_MI_STORE_DATA_IMM,
GFX8_MI_STORE_DATA_IMM_length + 1 /* QWord write */,
GFX8_MI_STORE_DATA_IMM,
.Address = secondary->return_addr)
+ (GEN8_MI_STORE_DATA_IMM_ImmediateData_start / 8);
+ (GFX8_MI_STORE_DATA_IMM_ImmediateData_start / 8);
emit_batch_buffer_start(primary, first_bbo->bo, 0);
@ -1822,7 +1822,7 @@ setup_empty_execbuf(struct anv_execbuf *execbuf, struct anv_queue *queue)
.buffers_ptr = (uintptr_t) execbuf->objects,
.buffer_count = execbuf->bo_count,
.batch_start_offset = 0,
.batch_len = 8, /* GEN7_MI_BATCH_BUFFER_END and NOOP */
.batch_len = 8, /* GFX7_MI_BATCH_BUFFER_END and NOOP */
.flags = I915_EXEC_HANDLE_LUT | queue->exec_flags | I915_EXEC_NO_RELOC,
.rsvd1 = device->context_id,
.rsvd2 = 0,

6
src/intel/vulkan/anv_device.c
View file

@ -1490,7 +1490,7 @@ void anv_GetPhysicalDeviceFeatures2(
* BSpec section "Multisample ModesState" table for "AA Line Support
* Requirements":
*
* GEN10:BUG:######## NUM_MULTISAMPLES == 1
* GFX10:BUG:######## NUM_MULTISAMPLES == 1
*
* Fortunately, this isn't a case most people care about.
*/
@ -2747,8 +2747,8 @@ anv_device_init_trivial_batch(struct anv_device *device)
.end = device->trivial_batch_bo->map + 4096,
};
anv_batch_emit(&batch, GEN7_MI_BATCH_BUFFER_END, bbe);
anv_batch_emit(&batch, GEN7_MI_NOOP, noop);
anv_batch_emit(&batch, GFX7_MI_BATCH_BUFFER_END, bbe);
anv_batch_emit(&batch, GFX7_MI_NOOP, noop);
if (!device->info.has_llc)
gen_clflush_range(batch.start, batch.next - batch.start);

38
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -2179,7 +2179,7 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
* 3DPRIMITIVE when needed anyway.
*/
anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
lrm.RegisterAddress = 0x243C; /* GEN7_3DPRIM_START_INSTANCE */
lrm.RegisterAddress = 0x243C; /* GFX7_3DPRIM_START_INSTANCE */
lrm.MemoryAddress = cmd_buffer->device->workaround_address;
}
}
@ -3764,12 +3764,12 @@ void genX(CmdDrawIndexed)(
}
/* Auto-Draw / Indirect Registers */
#define GEN7_3DPRIM_END_OFFSET 0x2420
#define GEN7_3DPRIM_START_VERTEX 0x2430
#define GEN7_3DPRIM_VERTEX_COUNT 0x2434
#define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
#define GEN7_3DPRIM_START_INSTANCE 0x243C
#define GEN7_3DPRIM_BASE_VERTEX 0x2440
#define GFX7_3DPRIM_END_OFFSET 0x2420
#define GFX7_3DPRIM_START_VERTEX 0x2430
#define GFX7_3DPRIM_VERTEX_COUNT 0x2434
#define GFX7_3DPRIM_INSTANCE_COUNT 0x2438
#define GFX7_3DPRIM_START_INSTANCE 0x243C
#define GFX7_3DPRIM_BASE_VERTEX 0x2440
void genX(CmdDrawIndirectByteCountEXT)(
VkCommandBuffer commandBuffer,
@ -3824,12 +3824,12 @@ void genX(CmdDrawIndirectByteCountEXT)(
if (counterOffset)
count = mi_isub(&b, count, mi_imm(counterOffset));
count = mi_udiv32_imm(&b, count, vertexStride);
mi_store(&b, mi_reg32(GEN7_3DPRIM_VERTEX_COUNT), count);
mi_store(&b, mi_reg32(GFX7_3DPRIM_VERTEX_COUNT), count);
mi_store(&b, mi_reg32(GEN7_3DPRIM_START_VERTEX), mi_imm(firstVertex));
mi_store(&b, mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT), mi_imm(instanceCount));
mi_store(&b, mi_reg32(GEN7_3DPRIM_START_INSTANCE), mi_imm(firstInstance));
mi_store(&b, mi_reg32(GEN7_3DPRIM_BASE_VERTEX), mi_imm(0));
mi_store(&b, mi_reg32(GFX7_3DPRIM_START_VERTEX), mi_imm(firstVertex));
mi_store(&b, mi_reg32(GFX7_3DPRIM_INSTANCE_COUNT), mi_imm(instanceCount));
mi_store(&b, mi_reg32(GFX7_3DPRIM_START_INSTANCE), mi_imm(firstInstance));
mi_store(&b, mi_reg32(GFX7_3DPRIM_BASE_VERTEX), mi_imm(0));
anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
prim.IndirectParameterEnable = true;
@ -3849,7 +3849,7 @@ load_indirect_parameters(struct anv_cmd_buffer *cmd_buffer,
struct mi_builder b;
mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
mi_store(&b, mi_reg32(GEN7_3DPRIM_VERTEX_COUNT),
mi_store(&b, mi_reg32(GFX7_3DPRIM_VERTEX_COUNT),
mi_mem32(anv_address_add(addr, 0)));
struct mi_value instance_count = mi_mem32(anv_address_add(addr, 4));
@ -3862,20 +3862,20 @@ load_indirect_parameters(struct anv_cmd_buffer *cmd_buffer,
"MI_MATH is not supported on Ivy Bridge");
#endif
}
mi_store(&b, mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT), instance_count);
mi_store(&b, mi_reg32(GFX7_3DPRIM_INSTANCE_COUNT), instance_count);
mi_store(&b, mi_reg32(GEN7_3DPRIM_START_VERTEX),
mi_store(&b, mi_reg32(GFX7_3DPRIM_START_VERTEX),
mi_mem32(anv_address_add(addr, 8)));
if (indexed) {
mi_store(&b, mi_reg32(GEN7_3DPRIM_BASE_VERTEX),
mi_store(&b, mi_reg32(GFX7_3DPRIM_BASE_VERTEX),
mi_mem32(anv_address_add(addr, 12)));
mi_store(&b, mi_reg32(GEN7_3DPRIM_START_INSTANCE),
mi_store(&b, mi_reg32(GFX7_3DPRIM_START_INSTANCE),
mi_mem32(anv_address_add(addr, 16)));
} else {
mi_store(&b, mi_reg32(GEN7_3DPRIM_START_INSTANCE),
mi_store(&b, mi_reg32(GFX7_3DPRIM_START_INSTANCE),
mi_mem32(anv_address_add(addr, 12)));
mi_store(&b, mi_reg32(GEN7_3DPRIM_BASE_VERTEX), mi_imm(0));
mi_store(&b, mi_reg32(GFX7_3DPRIM_BASE_VERTEX), mi_imm(0));
}
}

4
src/intel/vulkan/genX_pipeline.c
View file

@ -289,7 +289,7 @@ genX(emit_urb_setup)(struct anv_device *device, struct anv_batch *batch,
* 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
* needs to be sent before any combination of VS associated 3DSTATE."
*/
anv_batch_emit(batch, GEN7_PIPE_CONTROL, pc) {
anv_batch_emit(batch, GFX7_PIPE_CONTROL, pc) {
pc.DepthStallEnable = true;
pc.PostSyncOperation = WriteImmediateData;
pc.Address = device->workaround_address;
@ -705,7 +705,7 @@ emit_rs_state(struct anv_graphics_pipeline *pipeline,
raster.ScissorRectangleEnable = true;
#if GFX_VER >= 9
/* GEN9+ splits ViewportZClipTestEnable into near and far enable bits */
/* GFX9+ splits ViewportZClipTestEnable into near and far enable bits */
raster.ViewportZFarClipTestEnable = pipeline->depth_clip_enable;
raster.ViewportZNearClipTestEnable = pipeline->depth_clip_enable;
#elif GFX_VER >= 8

12
src/intel/vulkan/gfx7_cmd_buffer.c
View file

@ -70,7 +70,7 @@ gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
* 0, the clamps below produce 0 for xmin, ymin, xmax, ymax, which isn't
* what we want. Just special case empty clips and produce a canonical
* empty clip. */
static const struct GEN7_SCISSOR_RECT empty_scissor = {
static const struct GFX7_SCISSOR_RECT empty_scissor = {
.ScissorRectangleYMin = 1,
.ScissorRectangleXMin = 1,
.ScissorRectangleYMax = 0,
@ -103,7 +103,7 @@ gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
x_max = clamp_int64((uint64_t) x_max, 0, fb->width - 1);
}
struct GEN7_SCISSOR_RECT scissor = {
struct GFX7_SCISSOR_RECT scissor = {
.ScissorRectangleYMin = y_min,
.ScissorRectangleXMin = x_min,
.ScissorRectangleYMax = y_max,
@ -111,15 +111,15 @@ gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
};
if (s->extent.width <= 0 || s->extent.height <= 0) {
GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8,
GFX7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8,
&empty_scissor);
} else {
GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8, &scissor);
GFX7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8, &scissor);
}
}
anv_batch_emit(&cmd_buffer->batch,
GEN7_3DSTATE_SCISSOR_STATE_POINTERS, ssp) {
GFX7_3DSTATE_SCISSOR_STATE_POINTERS, ssp) {
ssp.ScissorRectPointer = scissor_state.offset;
}
}
@ -313,7 +313,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
uint32_t offset = cmd_buffer->state.gfx.gen7.index_offset;
#if GFX_VERx10 == 75
anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF, vf) {
anv_batch_emit(&cmd_buffer->batch, GFX75_3DSTATE_VF, vf) {
vf.IndexedDrawCutIndexEnable = pipeline->primitive_restart;
vf.CutIndex = cmd_buffer->state.restart_index;
}

4
src/mesa/drivers/dri/i965/brw_batch.c
View file

@ -1104,7 +1104,7 @@ load_sized_register_mem(struct brw_context *brw,
if (devinfo->ver >= 8) {
BEGIN_BATCH(4 * size);
for (i = 0; i < size; i++) {
OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (4 - 2));
OUT_BATCH(GFX7_MI_LOAD_REGISTER_MEM | (4 - 2));
OUT_BATCH(reg + i * 4);
OUT_RELOC64(bo, 0, offset + i * 4);
}
@ -1112,7 +1112,7 @@ load_sized_register_mem(struct brw_context *brw,
} else {
BEGIN_BATCH(3 * size);
for (i = 0; i < size; i++) {
OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
OUT_BATCH(GFX7_MI_LOAD_REGISTER_MEM | (3 - 2));
OUT_BATCH(reg + i * 4);
OUT_RELOC(bo, 0, offset + i * 4);
}

6
src/mesa/drivers/dri/i965/brw_binding_tables.c
View file

@ -280,9 +280,9 @@ gen6_upload_binding_table_pointers(struct brw_context *brw)
{
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 |
GEN6_BINDING_TABLE_MODIFY_VS |
GEN6_BINDING_TABLE_MODIFY_GS |
GEN6_BINDING_TABLE_MODIFY_PS |
GFX6_BINDING_TABLE_MODIFY_VS |
GFX6_BINDING_TABLE_MODIFY_GS |
GFX6_BINDING_TABLE_MODIFY_PS |
(4 - 2));
OUT_BATCH(brw->vs.base.bind_bo_offset); /* vs */
if (brw->ff_gs.prog_active)

2
src/mesa/drivers/dri/i965/brw_conditional_render.c
View file

@ -117,7 +117,7 @@ set_predicate_for_result(struct brw_context *brw,
load_op = MI_PREDICATE_LOADOP_LOADINV;
BEGIN_BATCH(1);
OUT_BATCH(GEN7_MI_PREDICATE |
OUT_BATCH(GFX7_MI_PREDICATE |
load_op |
MI_PREDICATE_COMBINEOP_SET |
MI_PREDICATE_COMPAREOP_SRCS_EQUAL);

2
src/mesa/drivers/dri/i965/brw_context.c
View file

@ -754,7 +754,7 @@ brw_initialize_context_constants(struct brw_context *brw)
/* ARB_viewport_array, OES_viewport_array */
if (devinfo->ver >= 6) {
ctx->Const.MaxViewports = GEN6_NUM_VIEWPORTS;
ctx->Const.MaxViewports = GFX6_NUM_VIEWPORTS;
ctx->Const.ViewportSubpixelBits = 8;
/* Cast to float before negating because MaxViewportWidth is unsigned.

6
src/mesa/drivers/dri/i965/brw_context.h
View file

@ -90,7 +90,7 @@ extern "C" {
* R0 - GRF register 0. Typically holds control information used when
* sending messages to other threads.
*
* EU or GEN4 EU: The name of the programmable subsystem of the
* EU or GFX4 EU: The name of the programmable subsystem of the
* i965 hardware. Threads are executed by the EU, the registers
* described above are part of the EU architecture.
*
@ -172,8 +172,8 @@ enum brw_cache_id {
};
enum gen9_astc5x5_wa_tex_type {
GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5 = 1 << 0,
GEN9_ASTC5X5_WA_TEX_TYPE_AUX = 1 << 1,
GFX9_ASTC5X5_WA_TEX_TYPE_ASTC5x5 = 1 << 0,
GFX9_ASTC5X5_WA_TEX_TYPE_AUX = 1 << 1,
};
enum brw_state_id {

1498
src/mesa/drivers/dri/i965/brw_defines.h
View file

File diff suppressed because it is too large Load diff

56
src/mesa/drivers/dri/i965/brw_draw.c
View file

@ -179,14 +179,14 @@ brw_emit_prim(struct brw_context *brw,
if (is_indexed) {
vertex_access_type = devinfo->ver >= 7 ?
GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM :
GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM;
GFX7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM :
GFX4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM;
start_vertex_location += brw->ib.start_vertex_offset;
base_vertex_location += brw->vb.start_vertex_bias;
} else {
vertex_access_type = devinfo->ver >= 7 ?
GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL :
GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL;
GFX7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL :
GFX4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL;
start_vertex_location += brw->vb.start_vertex_bias;
}
@ -210,20 +210,20 @@ brw_emit_prim(struct brw_context *brw,
/* If indirect, emit a bunch of loads from the indirect BO. */
if (xfb_obj) {
indirect_flag = GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE;
indirect_flag = GFX7_3DPRIM_INDIRECT_PARAMETER_ENABLE;
brw_load_register_mem(brw, GEN7_3DPRIM_VERTEX_COUNT,
brw_load_register_mem(brw, GFX7_3DPRIM_VERTEX_COUNT,
xfb_obj->prim_count_bo,
stream * sizeof(uint32_t));
BEGIN_BATCH(9);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (9 - 2));
OUT_BATCH(GEN7_3DPRIM_INSTANCE_COUNT);
OUT_BATCH(GFX7_3DPRIM_INSTANCE_COUNT);
OUT_BATCH(num_instances);
OUT_BATCH(GEN7_3DPRIM_START_VERTEX);
OUT_BATCH(GFX7_3DPRIM_START_VERTEX);
OUT_BATCH(0);
OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX);
OUT_BATCH(GFX7_3DPRIM_BASE_VERTEX);
OUT_BATCH(0);
OUT_BATCH(GEN7_3DPRIM_START_INSTANCE);
OUT_BATCH(GFX7_3DPRIM_START_INSTANCE);
OUT_BATCH(0);
ADVANCE_BATCH();
} else if (is_indirect) {
@ -232,24 +232,24 @@ brw_emit_prim(struct brw_context *brw,
brw_buffer_object(indirect_buffer),
indirect_offset, 5 * sizeof(GLuint), false);
indirect_flag = GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE;
indirect_flag = GFX7_3DPRIM_INDIRECT_PARAMETER_ENABLE;
brw_load_register_mem(brw, GEN7_3DPRIM_VERTEX_COUNT, bo,
brw_load_register_mem(brw, GFX7_3DPRIM_VERTEX_COUNT, bo,
indirect_offset + 0);
brw_load_register_mem(brw, GEN7_3DPRIM_INSTANCE_COUNT, bo,
brw_load_register_mem(brw, GFX7_3DPRIM_INSTANCE_COUNT, bo,
indirect_offset + 4);
brw_load_register_mem(brw, GEN7_3DPRIM_START_VERTEX, bo,
brw_load_register_mem(brw, GFX7_3DPRIM_START_VERTEX, bo,
indirect_offset + 8);
if (is_indexed) {
brw_load_register_mem(brw, GEN7_3DPRIM_BASE_VERTEX, bo,
brw_load_register_mem(brw, GFX7_3DPRIM_BASE_VERTEX, bo,
indirect_offset + 12);
brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
brw_load_register_mem(brw, GFX7_3DPRIM_START_INSTANCE, bo,
indirect_offset + 16);
} else {
brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
brw_load_register_mem(brw, GFX7_3DPRIM_START_INSTANCE, bo,
indirect_offset + 12);
brw_load_register_imm32(brw, GEN7_3DPRIM_BASE_VERTEX, 0);
brw_load_register_imm32(brw, GFX7_3DPRIM_BASE_VERTEX, 0);
}
} else {
indirect_flag = 0;
@ -260,13 +260,13 @@ brw_emit_prim(struct brw_context *brw,
if (devinfo->ver >= 7) {
const int predicate_enable =
(brw->predicate.state == BRW_PREDICATE_STATE_USE_BIT)
? GEN7_3DPRIM_PREDICATE_ENABLE : 0;
? GFX7_3DPRIM_PREDICATE_ENABLE : 0;
OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2) | indirect_flag | predicate_enable);
OUT_BATCH(hw_prim | vertex_access_type);
} else {
OUT_BATCH(CMD_3D_PRIM << 16 | (6 - 2) |
hw_prim << GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT |
hw_prim << GFX4_3DPRIM_TOPOLOGY_TYPE_SHIFT |
vertex_access_type);
}
OUT_BATCH(verts_per_instance);
@ -435,10 +435,10 @@ gen9_apply_astc5x5_wa_flush(struct brw_context *brw,
{
assert(brw->screen->devinfo.ver == 9);
if (((brw->gen9_astc5x5_wa_tex_mask & GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5) &&
(curr_mask & GEN9_ASTC5X5_WA_TEX_TYPE_AUX)) ||
((brw->gen9_astc5x5_wa_tex_mask & GEN9_ASTC5X5_WA_TEX_TYPE_AUX) &&
(curr_mask & GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5))) {
if (((brw->gen9_astc5x5_wa_tex_mask & GFX9_ASTC5X5_WA_TEX_TYPE_ASTC5x5) &&
(curr_mask & GFX9_ASTC5X5_WA_TEX_TYPE_AUX)) ||
((brw->gen9_astc5x5_wa_tex_mask & GFX9_ASTC5X5_WA_TEX_TYPE_AUX) &&
(curr_mask & GFX9_ASTC5X5_WA_TEX_TYPE_ASTC5x5))) {
brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL);
brw_emit_pipe_control_flush(brw, PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
}
@ -451,11 +451,11 @@ gen9_astc5x5_wa_bits(mesa_format format, enum isl_aux_usage aux_usage)
{
if (aux_usage != ISL_AUX_USAGE_NONE &&
aux_usage != ISL_AUX_USAGE_MCS)
return GEN9_ASTC5X5_WA_TEX_TYPE_AUX;
return GFX9_ASTC5X5_WA_TEX_TYPE_AUX;
if (format == MESA_FORMAT_RGBA_ASTC_5x5 ||
format == MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5)
return GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5;
return GFX9_ASTC5X5_WA_TEX_TYPE_ASTC5x5;
return 0;
}
@ -1207,11 +1207,11 @@ brw_draw_prims(struct gl_context *ctx,
BEGIN_BATCH(1);
if (i == 0 && brw->predicate.state != BRW_PREDICATE_STATE_USE_BIT) {
OUT_BATCH(GEN7_MI_PREDICATE | MI_PREDICATE_LOADOP_LOADINV |
OUT_BATCH(GFX7_MI_PREDICATE | MI_PREDICATE_LOADOP_LOADINV |
MI_PREDICATE_COMBINEOP_SET |
MI_PREDICATE_COMPAREOP_SRCS_EQUAL);
} else {
OUT_BATCH(GEN7_MI_PREDICATE |
OUT_BATCH(GFX7_MI_PREDICATE |
MI_PREDICATE_LOADOP_LOAD | MI_PREDICATE_COMBINEOP_XOR |
MI_PREDICATE_COMPAREOP_SRCS_EQUAL);
}

2
src/mesa/drivers/dri/i965/brw_mipmap_tree.c
View file

@ -1916,7 +1916,7 @@ brw_miptree_texture_aux_usage(struct brw_context *brw,
* CCS or HiZ compressed textures. See gen9_apply_astc5x5_wa_flush() for
* details.
*/
if ((astc5x5_wa_bits & GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5) &&
if ((astc5x5_wa_bits & GFX9_ASTC5X5_WA_TEX_TYPE_ASTC5x5) &&
mt->aux_usage != ISL_AUX_USAGE_MCS)
return ISL_AUX_USAGE_NONE;

18
src/mesa/drivers/dri/i965/brw_misc_state.c
View file

@ -646,9 +646,9 @@ brw_emit_hashing_mode(struct brw_context *brw, unsigned width,
* single slice hashing block is minimal, largely eliminating this
* effect.
*/
GEN9_SLICE_HASHING_32x32,
GFX9_SLICE_HASHING_32x32,
/* Finest slice hashing mode available. */
GEN9_SLICE_HASHING_NORMAL
GFX9_SLICE_HASHING_NORMAL
};
const uint32_t subslice_hashing[] = {
/* The 16x16 subslice hashing mode is used on non-LLC platforms to
@ -658,10 +658,10 @@ brw_emit_hashing_mode(struct brw_context *brw, unsigned width,
* cost of greater subslice imbalance for primitives of dimensions
* approximately intermediate between 16x4 and 16x16.
*/
(devinfo->has_llc ? GEN9_SUBSLICE_HASHING_16x4 :
GEN9_SUBSLICE_HASHING_16x16),
(devinfo->has_llc ? GFX9_SUBSLICE_HASHING_16x4 :
GFX9_SUBSLICE_HASHING_16x16),
/* Finest subslice hashing mode available. */
GEN9_SUBSLICE_HASHING_8x4
GFX9_SUBSLICE_HASHING_8x4
};
/* Dimensions of the smallest hashing block of a given hashing mode. If
* the rendering area is smaller than this there can't possibly be any
@ -677,14 +677,14 @@ brw_emit_hashing_mode(struct brw_context *brw, unsigned width,
if (width > min_size[idx][0] || height > min_size[idx][1]) {
const uint32_t gt_mode =
(devinfo->num_slices == 1 ? 0 :
GEN9_SLICE_HASHING_MASK_BITS | slice_hashing[idx]) |
GEN9_SUBSLICE_HASHING_MASK_BITS | subslice_hashing[idx];
GFX9_SLICE_HASHING_MASK_BITS | slice_hashing[idx]) |
GFX9_SUBSLICE_HASHING_MASK_BITS | subslice_hashing[idx];
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_STALL_AT_SCOREBOARD |
PIPE_CONTROL_CS_STALL);
brw_load_register_imm32(brw, GEN7_GT_MODE, gt_mode);
brw_load_register_imm32(brw, GFX7_GT_MODE, gt_mode);
brw->current_hash_scale = scale;
}
@ -830,7 +830,7 @@ brw_upload_state_base_address(struct brw_context *brw)
}
ADVANCE_BATCH();
} else if (devinfo->ver >= 6) {
uint8_t mocs = devinfo->ver == 7 ? GEN7_MOCS_L3 : 0;
uint8_t mocs = devinfo->ver == 7 ? GFX7_MOCS_L3 : 0;
BEGIN_BATCH(10);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));

2
src/mesa/drivers/dri/i965/brw_pipe_control.c
View file

@ -338,7 +338,7 @@ brw_emit_end_of_pipe_sync(struct brw_context *brw, uint32_t flags)
* always re-load all of the indirect draw registers right before
* 3DPRIMITIVE when needed anyway.
*/
brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE,
brw_load_register_mem(brw, GFX7_3DPRIM_START_INSTANCE,
brw->workaround_bo, brw->workaround_bo_offset);
}
} else {

4
src/mesa/drivers/dri/i965/brw_screen.c
View file

@ -2099,7 +2099,7 @@ brw_detect_pipelined_so(struct brw_screen *screen)
* statistics registers), and we already reset it to zero before using it.
*/
return brw_detect_pipelined_register(screen,
GEN7_SO_WRITE_OFFSET(0),
GFX7_SO_WRITE_OFFSET(0),
0x1337d0d0,
false);
}
@ -2845,7 +2845,7 @@ brw_allocate_buffer(__DRIscreen *dri_screen,
if (buffer == NULL)
return NULL;
/* The front and back buffers are color buffers, which are X tiled. GEN9+
/* The front and back buffers are color buffers, which are X tiled. GFX9+
* supports Y tiled and compressed buffers, but there is no way to plumb that
* through to here. */
uint32_t pitch;

2
src/mesa/drivers/dri/i965/brw_state.h
View file

@ -365,7 +365,7 @@ void gen11_init_atoms(struct brw_context *brw);
* On Ivybridge, the PTEs do have a cache-in-L3 bit, so setting MOCS to 0
* may still respect that.
*/
#define GEN7_MOCS_L3 1
#define GFX7_MOCS_L3 1
/* Ivybridge only: cache in LLC.
* Specifying zero here means to use the PTE values set by the kernel;

34
src/mesa/drivers/dri/i965/brw_state_upload.c
View file

@ -59,11 +59,11 @@ brw_enable_obj_preemption(struct brw_context *brw, bool enable)
brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH);
bool replay_mode = enable ?
GEN9_REPLAY_MODE_MIDOBJECT : GEN9_REPLAY_MODE_MIDBUFFER;
GFX9_REPLAY_MODE_MIDOBJECT : GFX9_REPLAY_MODE_MIDBUFFER;
/* enable object level preemption */
brw_load_register_imm32(brw, CS_CHICKEN1,
replay_mode | GEN9_REPLAY_MODE_MASK);
replay_mode | GFX9_REPLAY_MODE_MASK);
brw->object_preemption = enable;
}
@ -77,7 +77,7 @@ brw_upload_gen11_slice_hashing_state(struct brw_context *brw)
if (subslices_delta == 0)
return;
unsigned size = GEN11_SLICE_HASH_TABLE_length * 4;
unsigned size = GFX11_SLICE_HASH_TABLE_length * 4;
uint32_t hash_address;
uint32_t *map = brw_state_batch(brw, size, 64, &hash_address);
@ -115,7 +115,7 @@ brw_upload_gen11_slice_hashing_state(struct brw_context *brw)
* pixel pipe 1. When pixel pipe 0 has more subslices, then a similar table
* with 0's and 1's inverted is used.
*/
for (int i = 0; i < GEN11_SLICE_HASH_TABLE_length; i++) {
for (int i = 0; i < GFX11_SLICE_HASH_TABLE_length; i++) {
uint32_t dw = 0;
for (int j = 0; j < 8; j++) {
@ -172,7 +172,7 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
* headerless sampler messages are not allowed for pre-emptable
* contexts. Set the bit 5 to 1 to allow them.
*/
brw_load_register_imm32(brw, GEN11_SAMPLER_MODE,
brw_load_register_imm32(brw, GFX11_SAMPLER_MODE,
HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS_MASK |
HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS);
@ -187,30 +187,30 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
* in L3CNTLREG register. The default setting of the bit is not the
* desirable behavior.
*/
brw_load_register_imm32(brw, GEN8_L3CNTLREG,
GEN8_L3CNTLREG_EDBC_NO_HANG);
brw_load_register_imm32(brw, GFX8_L3CNTLREG,
GFX8_L3CNTLREG_EDBC_NO_HANG);
}
/* hardware specification recommends disabling repacking for
* the compatibility with decompression mechanism in display controller.
*/
if (devinfo->disable_ccs_repack) {
brw_load_register_imm32(brw, GEN7_CACHE_MODE_0,
GEN11_DISABLE_REPACKING_FOR_COMPRESSION |
REG_MASK(GEN11_DISABLE_REPACKING_FOR_COMPRESSION));
brw_load_register_imm32(brw, GFX7_CACHE_MODE_0,
GFX11_DISABLE_REPACKING_FOR_COMPRESSION |
REG_MASK(GFX11_DISABLE_REPACKING_FOR_COMPRESSION));
}
if (devinfo->ver == 9) {
/* Recommended optimizations for Victim Cache eviction and floating
* point blending.
*/
brw_load_register_imm32(brw, GEN7_CACHE_MODE_1,
REG_MASK(GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE) |
REG_MASK(GEN9_MSC_RAW_HAZARD_AVOIDANCE_BIT) |
REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) |
GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE |
GEN9_MSC_RAW_HAZARD_AVOIDANCE_BIT |
GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC);
brw_load_register_imm32(brw, GFX7_CACHE_MODE_1,
REG_MASK(GFX9_FLOAT_BLEND_OPTIMIZATION_ENABLE) |
REG_MASK(GFX9_MSC_RAW_HAZARD_AVOIDANCE_BIT) |
REG_MASK(GFX9_PARTIAL_RESOLVE_DISABLE_IN_VC) |
GFX9_FLOAT_BLEND_OPTIMIZATION_ENABLE |
GFX9_MSC_RAW_HAZARD_AVOIDANCE_BIT |
GFX9_PARTIAL_RESOLVE_DISABLE_IN_VC);
}
if (devinfo->ver >= 8) {

2
src/mesa/drivers/dri/i965/brw_surface_formats.c
View file

@ -503,7 +503,7 @@ translate_tex_format(struct brw_context *brw,
* processing sRGBs, which are incompatible with this mode.
*/
if (ctx->Extensions.KHR_texture_compression_astc_hdr)
isl_fmt |= GEN9_SURFACE_ASTC_HDR_FORMAT_BIT;
isl_fmt |= GFX9_SURFACE_ASTC_HDR_FORMAT_BIT;
return isl_fmt;
}

2
src/mesa/drivers/dri/i965/brw_urb.c
View file

@ -47,7 +47,7 @@
* Manages the division of the URB space between the various fixed-function
* units.
*
* See the Thread Initiation Management section of the GEN4 B-Spec, and
* See the Thread Initiation Management section of the GFX4 B-Spec, and
* the individual *_STATE structures for restrictions on numbers of
* entries and threads.
*/

2
src/mesa/drivers/dri/i965/brw_vs.c
View file

@ -177,7 +177,7 @@ brw_codegen_vs_prog(struct brw_context *brw,
}
/* Emit GEN4 code.
/* Emit GFX4 code.
*/
struct brw_compile_vs_params params = {
.nir = nir,

4
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
View file

@ -56,7 +56,7 @@
#include "brw_wm.h"
static const uint32_t wb_mocs[] = {
[7] = GEN7_MOCS_L3,
[7] = GFX7_MOCS_L3,
[8] = BDW_MOCS_WB,
[9] = SKL_MOCS_WB,
[10] = CNL_MOCS_WB,
@ -64,7 +64,7 @@ static const uint32_t wb_mocs[] = {
};
static const uint32_t pte_mocs[] = {
[7] = GEN7_MOCS_L3,
[7] = GFX7_MOCS_L3,
[8] = BDW_MOCS_PTE,
[9] = SKL_MOCS_PTE,
[10] = CNL_MOCS_PTE,

2
src/mesa/drivers/dri/i965/genX_blorp_exec.c
View file

@ -195,7 +195,7 @@ blorp_alloc_vertex_buffer(struct blorp_batch *batch, uint32_t size,
#elif GFX_VER == 8
.mocs = BDW_MOCS_WB,
#elif GFX_VER == 7
.mocs = GEN7_MOCS_L3,
.mocs = GFX7_MOCS_L3,
#elif GFX_VER > 6
#error "Missing MOCS setting!"
#endif

12
src/mesa/drivers/dri/i965/genX_state_upload.c
View file

@ -271,7 +271,7 @@ genX(emit_vertex_buffer_state)(struct brw_context *brw,
#elif GFX_VER == 8
.MOCS = BDW_MOCS_WB,
#elif GFX_VER == 7
.MOCS = GEN7_MOCS_L3,
.MOCS = GFX7_MOCS_L3,
#endif
};
@ -2621,7 +2621,7 @@ genX(upload_gs_state)(struct brw_context *brw)
gs.ControlDataFormat = gs_prog_data->control_data_format;
#endif
/* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
/* Note: the meaning of the GFX7_GS_REORDER_TRAILING bit changes between
* Ivy Bridge and Haswell.
*
* On Ivy Bridge, setting this bit causes the vertices of a triangle
@ -2657,7 +2657,7 @@ genX(upload_gs_state)(struct brw_context *brw)
if (gs_prog->info.has_transform_feedback_varyings)
gs.SVBIPayloadEnable = _mesa_is_xfb_active_and_unpaused(ctx);
/* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it
/* GFX6_GS_SPF_MODE and GFX6_GS_VECTOR_MASK_ENABLE are enabled as it
* was previously done for gen6.
*
* TODO: test with both disabled to see if the HW is behaving
@ -3082,7 +3082,7 @@ genX(upload_push_constant_packets)(struct brw_context *brw)
const struct gen_device_info *devinfo = &brw->screen->devinfo;
struct gl_context *ctx = &brw->ctx;
UNUSED uint32_t mocs = GFX_VER < 8 ? GEN7_MOCS_L3 : 0;
UNUSED uint32_t mocs = GFX_VER < 8 ? GFX7_MOCS_L3 : 0;
struct brw_stage_state *stage_states[] = {
&brw->vs.base,
@ -4712,8 +4712,8 @@ genX(upload_ps_extra)(struct brw_context *brw)
* in the 3DSTATE_WM command on Gen7), and because in some cases it will
* determine whether the hardware skips execution of the fragment shader
* or not via the ThreadDispatchEnable signal. However if we know that
* GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
* GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
* GFX8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
* GFX8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
* difference so we may just disable it here.
*
* Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't

14
src/mesa/drivers/dri/i965/gfx6_queryobj.c
View file

@ -85,7 +85,7 @@ write_primitives_generated(struct brw_context *brw,
if (devinfo->ver >= 7 && stream > 0) {
brw_store_register_mem64(brw, query_bo,
GEN7_SO_PRIM_STORAGE_NEEDED(stream),
GFX7_SO_PRIM_STORAGE_NEEDED(stream),
idx * sizeof(uint64_t));
} else {
brw_store_register_mem64(brw, query_bo, CL_INVOCATION_COUNT,
@ -102,10 +102,10 @@ write_xfb_primitives_written(struct brw_context *brw,
brw_emit_mi_flush(brw);
if (devinfo->ver >= 7) {
brw_store_register_mem64(brw, bo, GEN7_SO_NUM_PRIMS_WRITTEN(stream),
brw_store_register_mem64(brw, bo, GFX7_SO_NUM_PRIMS_WRITTEN(stream),
idx * sizeof(uint64_t));
} else {
brw_store_register_mem64(brw, bo, GEN6_SO_NUM_PRIMS_WRITTEN,
brw_store_register_mem64(brw, bo, GFX6_SO_NUM_PRIMS_WRITTEN,
idx * sizeof(uint64_t));
}
}
@ -126,17 +126,17 @@ write_xfb_overflow_streams(struct gl_context *ctx,
if (devinfo->ver >= 7) {
brw_store_register_mem64(brw, bo,
GEN7_SO_NUM_PRIMS_WRITTEN(stream + i),
GFX7_SO_NUM_PRIMS_WRITTEN(stream + i),
g_idx * sizeof(uint64_t));
brw_store_register_mem64(brw, bo,
GEN7_SO_PRIM_STORAGE_NEEDED(stream + i),
GFX7_SO_PRIM_STORAGE_NEEDED(stream + i),
w_idx * sizeof(uint64_t));
} else {
brw_store_register_mem64(brw, bo,
GEN6_SO_NUM_PRIMS_WRITTEN,
GFX6_SO_NUM_PRIMS_WRITTEN,
g_idx * sizeof(uint64_t));
brw_store_register_mem64(brw, bo,
GEN6_SO_PRIM_STORAGE_NEEDED,
GFX6_SO_PRIM_STORAGE_NEEDED,
w_idx * sizeof(uint64_t));
}
}

4
src/mesa/drivers/dri/i965/gfx6_sol.c
View file

@ -302,12 +302,12 @@ brw_save_primitives_written_counters(struct brw_context *brw,
for (int i = 0; i < streams; i++) {
int offset = (streams * obj->counter.bo_end + i) * sizeof(uint64_t);
brw_store_register_mem64(brw, obj->prim_count_bo,
GEN7_SO_NUM_PRIMS_WRITTEN(i),
GFX7_SO_NUM_PRIMS_WRITTEN(i),
offset);
}
} else {
brw_store_register_mem64(brw, obj->prim_count_bo,
GEN6_SO_NUM_PRIMS_WRITTEN,
GFX6_SO_NUM_PRIMS_WRITTEN,
obj->counter.bo_end * sizeof(uint64_t));
}

8
src/mesa/drivers/dri/i965/gfx6_urb.c
View file

@ -83,10 +83,10 @@ gen6_upload_urb(struct brw_context *brw, unsigned vs_size,
BEGIN_BATCH(3);
OUT_BATCH(_3DSTATE_URB << 16 | (3 - 2));
OUT_BATCH(((vs_size - 1) << GEN6_URB_VS_SIZE_SHIFT) |
((brw->urb.nr_vs_entries) << GEN6_URB_VS_ENTRIES_SHIFT));
OUT_BATCH(((gs_size - 1) << GEN6_URB_GS_SIZE_SHIFT) |
((brw->urb.nr_gs_entries) << GEN6_URB_GS_ENTRIES_SHIFT));
OUT_BATCH(((vs_size - 1) << GFX6_URB_VS_SIZE_SHIFT) |
((brw->urb.nr_vs_entries) << GFX6_URB_VS_ENTRIES_SHIFT));
OUT_BATCH(((gs_size - 1) << GFX6_URB_GS_SIZE_SHIFT) |
((brw->urb.nr_gs_entries) << GFX6_URB_GS_ENTRIES_SHIFT));
ADVANCE_BATCH();
/* From the PRM Volume 2 part 1, section 1.4.7:

46
src/mesa/drivers/dri/i965/gfx7_l3_state.c
View file

@ -119,15 +119,15 @@ setup_l3_config(struct brw_context *brw, const struct intel_l3_config *cfg)
assert(!cfg->n[INTEL_L3P_IS] && !cfg->n[INTEL_L3P_C] && !cfg->n[INTEL_L3P_T]);
const unsigned imm_data = (
(devinfo->ver < 11 && has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) |
(devinfo->ver == 11 ? GEN11_L3CNTLREG_USE_FULL_WAYS : 0) |
SET_FIELD(cfg->n[INTEL_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
SET_FIELD(cfg->n[INTEL_L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
SET_FIELD(cfg->n[INTEL_L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
SET_FIELD(cfg->n[INTEL_L3P_ALL], GEN8_L3CNTLREG_ALL_ALLOC));
(devinfo->ver < 11 && has_slm ? GFX8_L3CNTLREG_SLM_ENABLE : 0) |
(devinfo->ver == 11 ? GFX11_L3CNTLREG_USE_FULL_WAYS : 0) |
SET_FIELD(cfg->n[INTEL_L3P_URB], GFX8_L3CNTLREG_URB_ALLOC) |
SET_FIELD(cfg->n[INTEL_L3P_RO], GFX8_L3CNTLREG_RO_ALLOC) |
SET_FIELD(cfg->n[INTEL_L3P_DC], GFX8_L3CNTLREG_DC_ALLOC) |
SET_FIELD(cfg->n[INTEL_L3P_ALL], GFX8_L3CNTLREG_ALL_ALLOC));
/* Set up the L3 partitioning. */
brw_load_register_imm32(brw, GEN8_L3CNTLREG, imm_data);
brw_load_register_imm32(brw, GFX8_L3CNTLREG, imm_data);
} else {
assert(!cfg->n[INTEL_L3P_ALL]);
@ -147,27 +147,27 @@ setup_l3_config(struct brw_context *brw, const struct intel_l3_config *cfg)
OUT_BATCH(MI_LOAD_REGISTER_IMM | (7 - 2));
/* Demote any clients with no ways assigned to LLC. */
OUT_BATCH(GEN7_L3SQCREG1);
OUT_BATCH(GFX7_L3SQCREG1);
OUT_BATCH((devinfo->is_haswell ? HSW_L3SQCREG1_SQGHPCI_DEFAULT :
devinfo->is_baytrail ? VLV_L3SQCREG1_SQGHPCI_DEFAULT :
IVB_L3SQCREG1_SQGHPCI_DEFAULT) |
(has_dc ? 0 : GEN7_L3SQCREG1_CONV_DC_UC) |
(has_is ? 0 : GEN7_L3SQCREG1_CONV_IS_UC) |
(has_c ? 0 : GEN7_L3SQCREG1_CONV_C_UC) |
(has_t ? 0 : GEN7_L3SQCREG1_CONV_T_UC));
(has_dc ? 0 : GFX7_L3SQCREG1_CONV_DC_UC) |
(has_is ? 0 : GFX7_L3SQCREG1_CONV_IS_UC) |
(has_c ? 0 : GFX7_L3SQCREG1_CONV_C_UC) |
(has_t ? 0 : GFX7_L3SQCREG1_CONV_T_UC));
/* Set up the L3 partitioning. */
OUT_BATCH(GEN7_L3CNTLREG2);
OUT_BATCH((has_slm ? GEN7_L3CNTLREG2_SLM_ENABLE : 0) |
SET_FIELD(cfg->n[INTEL_L3P_URB] - n0_urb, GEN7_L3CNTLREG2_URB_ALLOC) |
(urb_low_bw ? GEN7_L3CNTLREG2_URB_LOW_BW : 0) |
SET_FIELD(cfg->n[INTEL_L3P_ALL], GEN7_L3CNTLREG2_ALL_ALLOC) |
SET_FIELD(cfg->n[INTEL_L3P_RO], GEN7_L3CNTLREG2_RO_ALLOC) |
SET_FIELD(cfg->n[INTEL_L3P_DC], GEN7_L3CNTLREG2_DC_ALLOC));
OUT_BATCH(GEN7_L3CNTLREG3);
OUT_BATCH(SET_FIELD(cfg->n[INTEL_L3P_IS], GEN7_L3CNTLREG3_IS_ALLOC) |
SET_FIELD(cfg->n[INTEL_L3P_C], GEN7_L3CNTLREG3_C_ALLOC) |
SET_FIELD(cfg->n[INTEL_L3P_T], GEN7_L3CNTLREG3_T_ALLOC));
OUT_BATCH(GFX7_L3CNTLREG2);
OUT_BATCH((has_slm ? GFX7_L3CNTLREG2_SLM_ENABLE : 0) |
SET_FIELD(cfg->n[INTEL_L3P_URB] - n0_urb, GFX7_L3CNTLREG2_URB_ALLOC) |
(urb_low_bw ? GFX7_L3CNTLREG2_URB_LOW_BW : 0) |
SET_FIELD(cfg->n[INTEL_L3P_ALL], GFX7_L3CNTLREG2_ALL_ALLOC) |
SET_FIELD(cfg->n[INTEL_L3P_RO], GFX7_L3CNTLREG2_RO_ALLOC) |
SET_FIELD(cfg->n[INTEL_L3P_DC], GFX7_L3CNTLREG2_DC_ALLOC));
OUT_BATCH(GFX7_L3CNTLREG3);
OUT_BATCH(SET_FIELD(cfg->n[INTEL_L3P_IS], GFX7_L3CNTLREG3_IS_ALLOC) |
SET_FIELD(cfg->n[INTEL_L3P_C], GFX7_L3CNTLREG3_C_ALLOC) |
SET_FIELD(cfg->n[INTEL_L3P_T], GFX7_L3CNTLREG3_T_ALLOC));
ADVANCE_BATCH();

8
src/mesa/drivers/dri/i965/gfx7_sol_state.c
View file

@ -54,7 +54,7 @@ gen7_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
brw->batch.needs_sol_reset = true;
} else {
for (int i = 0; i < 4; i++) {
brw_load_register_imm32(brw, GEN7_SO_WRITE_OFFSET(i), 0);
brw_load_register_imm32(brw, GFX7_SO_WRITE_OFFSET(i), 0);
}
}
@ -112,7 +112,7 @@ gen7_pause_transform_feedback(struct gl_context *ctx,
for (int i = 0; i < 4; i++) {
BEGIN_BATCH(3);
OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
OUT_BATCH(GEN7_SO_WRITE_OFFSET(i));
OUT_BATCH(GFX7_SO_WRITE_OFFSET(i));
OUT_RELOC(brw_obj->offset_bo, RELOC_WRITE, i * sizeof(uint32_t));
ADVANCE_BATCH();
}
@ -138,8 +138,8 @@ gen7_resume_transform_feedback(struct gl_context *ctx,
/* Reload the SOL buffer offset registers. */
for (int i = 0; i < 4; i++) {
BEGIN_BATCH(3);
OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
OUT_BATCH(GEN7_SO_WRITE_OFFSET(i));
OUT_BATCH(GFX7_MI_LOAD_REGISTER_MEM | (3 - 2));
OUT_BATCH(GFX7_SO_WRITE_OFFSET(i));
OUT_RELOC(brw_obj->offset_bo, RELOC_WRITE, i * sizeof(uint32_t));
ADVANCE_BATCH();
}

14
src/mesa/drivers/dri/i965/gfx7_urb.c
View file

@ -147,23 +147,23 @@ gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size,
BEGIN_BATCH(10);
OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_VS << 16 | (2 - 2));
OUT_BATCH(vs_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
OUT_BATCH(vs_size | offset << GFX7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
offset += vs_size;
OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_HS << 16 | (2 - 2));
OUT_BATCH(hs_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
OUT_BATCH(hs_size | offset << GFX7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
offset += hs_size;
OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_DS << 16 | (2 - 2));
OUT_BATCH(ds_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
OUT_BATCH(ds_size | offset << GFX7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
offset += ds_size;
OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_GS << 16 | (2 - 2));
OUT_BATCH(gs_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
OUT_BATCH(gs_size | offset << GFX7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
offset += gs_size;
OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_PS << 16 | (2 - 2));
OUT_BATCH(fs_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
OUT_BATCH(fs_size | offset << GFX7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
ADVANCE_BATCH();
/* From p292 of the Ivy Bridge PRM (11.2.4 3DSTATE_PUSH_CONSTANT_ALLOC_PS):
@ -260,8 +260,8 @@ gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
assert(devinfo->ver != 10 || entry_size[i] % 3);
OUT_BATCH((_3DSTATE_URB_VS + i) << 16 | (2 - 2));
OUT_BATCH(entries[i] |
((entry_size[i] - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) |
(start[i] << GEN7_URB_STARTING_ADDRESS_SHIFT));
((entry_size[i] - 1) << GFX7_URB_ENTRY_SIZE_SHIFT) |
(start[i] << GFX7_URB_STARTING_ADDRESS_SHIFT));
}
ADVANCE_BATCH();
}

6
src/mesa/drivers/dri/i965/gfx8_depth_state.c
View file

@ -153,8 +153,8 @@ gen8_write_pma_stall_bits(struct brw_context *brw, uint32_t pma_stall_bits)
render_cache_flush);
/* CACHE_MODE_1 is a non-privileged register. */
brw_load_register_imm32(brw, GEN7_CACHE_MODE_1,
GEN8_HIZ_PMA_MASK_BITS |
brw_load_register_imm32(brw, GFX7_CACHE_MODE_1,
GFX8_HIZ_PMA_MASK_BITS |
pma_stall_bits );
/* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
@ -178,7 +178,7 @@ gen8_emit_pma_stall_workaround(struct brw_context *brw)
return;
if (pma_fix_enable(brw))
bits |= GEN8_HIZ_NP_PMA_FIX_ENABLE | GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE;
bits |= GFX8_HIZ_NP_PMA_FIX_ENABLE | GFX8_HIZ_NP_EARLY_Z_FAILS_DISABLE;
gen8_write_pma_stall_bits(brw, bits);
}

2
src/mesa/drivers/dri/i965/hsw_queryobj.c
View file

@ -392,7 +392,7 @@ set_predicate(struct brw_context *brw, struct brw_bo *query_bo)
/* predicate = !(query_availability == 0); */
BEGIN_BATCH(1);
OUT_BATCH(GEN7_MI_PREDICATE |
OUT_BATCH(GFX7_MI_PREDICATE |
MI_PREDICATE_LOADOP_LOADINV |
MI_PREDICATE_COMBINEOP_SET |
MI_PREDICATE_COMPAREOP_SRCS_EQUAL);

12
src/mesa/drivers/dri/i965/hsw_sol.c
View file

@ -64,7 +64,7 @@ save_prim_start_values(struct brw_context *brw,
/* Emit MI_STORE_REGISTER_MEM commands to write the values. */
for (int i = 0; i < BRW_MAX_XFB_STREAMS; i++) {
brw_store_register_mem64(brw, obj->prim_count_bo,
GEN7_SO_NUM_PRIMS_WRITTEN(i),
GFX7_SO_NUM_PRIMS_WRITTEN(i),
START_OFFSET + i * sizeof(uint64_t));
}
}
@ -99,7 +99,7 @@ tally_prims_written(struct brw_context *brw,
START_OFFSET + i * sizeof(uint64_t));
/* GPR2 = Ending Snapshot */
brw_load_register_reg64(brw, HSW_CS_GPR(2),
GEN7_SO_NUM_PRIMS_WRITTEN(i));
GFX7_SO_NUM_PRIMS_WRITTEN(i));
BEGIN_BATCH(9);
OUT_BATCH(HSW_MI_MATH | (9 - 2));
@ -173,7 +173,7 @@ hsw_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
BEGIN_BATCH(1 + 2 * BRW_MAX_XFB_STREAMS);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (1 + 2 * BRW_MAX_XFB_STREAMS - 2));
for (int i = 0; i < BRW_MAX_XFB_STREAMS; i++) {
OUT_BATCH(GEN7_SO_WRITE_OFFSET(i));
OUT_BATCH(GFX7_SO_WRITE_OFFSET(i));
OUT_BATCH(0);
}
ADVANCE_BATCH();
@ -207,7 +207,7 @@ hsw_pause_transform_feedback(struct gl_context *ctx,
for (int i = 0; i < BRW_MAX_XFB_STREAMS; i++) {
BEGIN_BATCH(3);
OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
OUT_BATCH(GEN7_SO_WRITE_OFFSET(i));
OUT_BATCH(GFX7_SO_WRITE_OFFSET(i));
OUT_RELOC(brw_obj->offset_bo, RELOC_WRITE, i * sizeof(uint32_t));
ADVANCE_BATCH();
}
@ -233,8 +233,8 @@ hsw_resume_transform_feedback(struct gl_context *ctx,
/* Reload the SOL buffer offset registers. */
for (int i = 0; i < BRW_MAX_XFB_STREAMS; i++) {
BEGIN_BATCH(3);
OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
OUT_BATCH(GEN7_SO_WRITE_OFFSET(i));
OUT_BATCH(GFX7_MI_LOAD_REGISTER_MEM | (3 - 2));
OUT_BATCH(GFX7_SO_WRITE_OFFSET(i));
OUT_RELOC(brw_obj->offset_bo, RELOC_WRITE, i * sizeof(uint32_t));
ADVANCE_BATCH();
}