fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-04-24 00:40:36 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

freedreno/drm-shim: Add support for faking other adreno chips.

Browse source 
I wanted to look at the effect of a core NIR change on a2xx codegen, but I
don't have any of those boards.  This could also prove useful for quickly
sanity-checking the compiler by running shader-db on it -- a2xx fails in a
few ways on glmark2, and a3xx-a5xx fails on glmark2 in a debug_assert
(which we don't have enabled in our dEQP runs).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4652>
This commit is contained in:
Eric Anholt 2020-04-17 17:18:25 -07:00 • committed by Marge Bot
parent cc23920746
commit c1e7c1f422
2 changed files with 124 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
src/freedreno/drm-shim/README.md
View file

@ -5,3 +5,6 @@ The submit ioctl is stubbed out to not execute anything.
Export `MESA_LOADER_DRIVER_OVERRIDE=msm
LD_PRELOAD=$prefix/lib/libfreedreno_noop_drm_shim.so`.
By default, a630 is exposed. The chip can be selected an enviornment
variable like `FD_GPU_ID=307"

124
src/freedreno/drm-shim/freedreno_noop.c
View file

@ -47,6 +47,14 @@ static struct msm_device msm = {
.next_offset = 0x1000,
};
struct msm_device_info {
uint32_t gpu_id;
uint32_t chip_id;
uint32_t gmem_size;
};
static const struct msm_device_info *device_info;
static int
msm_ioctl_noop(int fd, unsigned long request, void *arg)
{
@ -108,16 +116,16 @@ msm_ioctl_get_param(int fd, unsigned long request, void *arg)
switch (gp->param) {
case MSM_PARAM_GPU_ID:
gp->value = 630;
gp->value = device_info->gpu_id;
return 0;
case MSM_PARAM_GMEM_SIZE:
gp->value = 1024 * 1024;
gp->value = device_info->gmem_size;
return 0;
case MSM_PARAM_GMEM_BASE:
gp->value = 0x100000;
return 0;
case MSM_PARAM_CHIP_ID:
gp->value = (6 << 24) | (3 << 16) | (0 << 8) | (0xff << 0);
gp->value = device_info->chip_id;
return 0;
case MSM_PARAM_NR_RINGS:
gp->value = 1;
@ -165,6 +173,114 @@ static ioctl_fn_t driver_ioctls[] = {
[DRM_MSM_SUBMITQUEUE_QUERY] = msm_ioctl_noop,
};
#define CHIPID(maj, min, rev, pat) \
((maj << 24) | (min << 16) | (rev << 8) | (pat))
static const struct msm_device_info device_infos[] = {
{ /* First entry is default */
.gpu_id = 630,
.chip_id = CHIPID(6, 3, 0, 0xff),
.gmem_size = 1024 * 1024,
},
{
.gpu_id = 200,
.chip_id = CHIPID(2, 0, 0, 0),
.gmem_size = 256 * 1024,
},
{
.gpu_id = 201,
.chip_id = CHIPID(2, 0, 0, 1),
.gmem_size = 128 * 1024,
},
{
.gpu_id = 220,
.chip_id = CHIPID(2, 2, 0, 0xff),
.gmem_size = 512 * 1024,
},
{
.gpu_id = 305,
.chip_id = CHIPID(3, 0, 5, 0xff),
.gmem_size = 256 * 1024,
},
{
.gpu_id = 307,
.chip_id = CHIPID(3, 0, 6, 0),
.gmem_size = 128 * 1024,
},
{
.gpu_id = 320,
.chip_id = CHIPID(3, 2, 0xff, 0xff),
.gmem_size = 512 * 1024,
},
{
.gpu_id = 330,
.chip_id = CHIPID(3, 3, 0, 0xff),
.gmem_size = 1024 * 1024,
},
{
.gpu_id = 420,
.chip_id = CHIPID(4, 2, 0, 0xff),
.gmem_size = 1536 * 1024,
},
{
.gpu_id = 430,
.chip_id = CHIPID(4, 3, 0, 0xff),
.gmem_size = 1536 * 1024,
},
{
.gpu_id = 510,
.chip_id = CHIPID(5, 1, 0, 0xff),
.gmem_size = 256 * 1024,
},
{
.gpu_id = 530,
.chip_id = CHIPID(5, 3, 0, 2),
.gmem_size = 1024 * 1024,
},
{
.gpu_id = 540,
.chip_id = CHIPID(5, 4, 0, 2),
.gmem_size = 1024 * 1024,
},
{
.gpu_id = 618,
.chip_id = CHIPID(6, 1, 8, 0xff),
.gmem_size = 512 * 1024,
},
{
.gpu_id = 630,
.chip_id = CHIPID(6, 3, 0, 0xff),
.gmem_size = 1024 * 1024,
},
};
static void
msm_driver_get_device_info(void)
{
const char *env = getenv("FD_GPU_ID");
if (!env) {
device_info = &device_infos[0];
return;
}
int gpu_id = atoi(env);
for (int i = 0; i < ARRAY_SIZE(device_infos); i++) {
if (device_infos[i].gpu_id == gpu_id) {
device_info = &device_infos[i];
return;
}
}
fprintf(stderr, "FD_GPU_ID unrecognized, shim supports %d",
device_infos[0].gpu_id);
for (int i = 1; i < ARRAY_SIZE(device_infos); i++)
fprintf(stderr, ", %d", device_infos[i].gpu_id);
fprintf(stderr, "\n");
abort();
}
void
drm_shim_driver_init(void)
{
@ -178,6 +294,8 @@ drm_shim_driver_init(void)
shim_device.version_minor = 5;
shim_device.version_patchlevel = 0;
msm_driver_get_device_info();
drm_shim_override_file("OF_FULLNAME=/rdb/msm\n"
"OF_COMPATIBLE_N=1\n"
"OF_COMPATIBLE_0=qcom,adreno\n",