From c1e1cc9b014c744d6c1e385ca742886b084982c6 Mon Sep 17 00:00:00 2001
From: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Date: Wed, 4 Feb 2026 15:35:09 -0500
Subject: [PATCH] brw: lower mem access sizes even for UBOs

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40877>
---
 src/intel/compiler/brw/brw_nir.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/intel/compiler/brw/brw_nir.c b/src/intel/compiler/brw/brw_nir.c
index dff440e8b2f..d4552d19560 100644
--- a/src/intel/compiler/brw/brw_nir.c
+++ b/src/intel/compiler/brw/brw_nir.c
@@ -2555,6 +2555,7 @@ brw_vectorize_lower_mem_access(brw_pass_tracker *pt)
 
    nir_lower_mem_access_bit_sizes_options mem_access_options = {
       .modes = nir_var_mem_ssbo |
+               nir_var_mem_ubo |
                nir_var_mem_constant |
                nir_var_mem_task_payload |
                nir_var_shader_temp |