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intel/compiler: make sure swizzle is applied to if condition

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This fixes a hang in the following piglit test when GCM moves a
UBO load outside of the loop.

tests/shaders/ssa/fs-if-def-else-break.shader_test

The end NIR ends up looking like this:

	vec2 32 ssa_3 = intrinsic load_ubo (ssa_2, ssa_0) (0, 1073741824, 0, 0, 8)
	vec1 32 ssa_4 = mov ssa_3.x
	vec1 32 ssa_5 = inot ssa_3.y
	/* succs: block_1 */
	loop {
           ...
           if ssa_5 { }
        }

Fixes: 1edf67fc3f ("intel/fs: Generate if instructions with inverted conditions")

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12064>
(cherry picked from commit a654e39f15)
This commit is contained in:
Timothy Arceri 2021-07-29 12:14:16 +10:00 • committed by Eric Engestrom
parent 4bc27e13f5
commit c1df4a94fc
2 changed files with 2 additions and 1 deletions
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2
.pick_status.json
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@ -490,7 +490,7 @@
"description": "intel/compiler: make sure swizzle is applied to if condition",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "1edf67fc3f6b944935506146de02348afa1003ff"
},

1
src/intel/compiler/brw_fs_nir.cpp
View file

@ -353,6 +353,7 @@ fs_visitor::nir_emit_if(nir_if *if_stmt)
if (cond != NULL && cond->op == nir_op_inot) {
invert = true;
cond_reg = get_nir_src(cond->src[0].src);
cond_reg = offset(cond_reg, bld, cond->src[0].swizzle[0]);
} else {
invert = false;
cond_reg = get_nir_src(if_stmt->condition);