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anv/icl: Don't set float blend optimization bit in CACHE_MODE_SS

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CACHE_MODE_SS is not listed in gfxspecs table for user mode
non-privileged registers. So, making any changes from Mesa
will do nothing. Kernel is already setting this bit in
CACHE_MODE_SS register which is saved/restored to/from
the HW context image.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
This commit is contained in:
Anuj Phogat 2018-05-31 15:41:53 -07:00
parent 227dabc266
commit c1d8300117
1 changed files with 0 additions and 12 deletions
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12
src/intel/vulkan/genX_state.c
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@ -121,18 +121,6 @@ genX(init_device_state)(struct anv_device *device)
}
#endif
#if GEN_GEN == 10 || GEN_GEN == 11
uint32_t cache_mode_ss;
anv_pack_struct(&cache_mode_ss, GENX(CACHE_MODE_SS),
.FloatBlendOptimizationEnable = true,
.FloatBlendOptimizationEnableMask = true);
anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
lri.RegisterOffset = GENX(CACHE_MODE_SS_num);
lri.DataDWord = cache_mode_ss;
}
#endif
anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa);
anv_batch_emit(&batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {